CHAPTER 18:Sound Generator
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
415
3.4.
Relation between the DMA Transfer Update Enable Register (SGDER) and
DMA Settings
This section describes the relation between the DMA Transfer Update Enable Register (SGDER) and
DMA settings.
3.4.1.
The Number of DMA Transfers
DMA Transfer Update Enable Register (SGDER) determines the number of DMA transfer, once or twice.
If all of SGDER.ARE1, SGDER.ARE0, SGDER.FRE and SGDER.NRE are "0", or
all of SGDER.TCRE, SGDER.IDRE, SGDER.PCRE1 and SGDER.PCRE0 are "0",
the DMA transfer occurs only once. Otherwise, the DMA transfer occurs twice.
3.4.2.
DMA Transfer Size
The DMA transfer size (1 byte, 2 bytes or 4 bytes) depends on the setting of the DMA Transfer Update
Enable Register (SGDER).
The greater value of the following two becomes the DMA transfer size:
The value of SGDER.ARE1, SGDER.ARE0, SGDER.FRE, and SGDER.NRE,
The value of SGDER.TCRE, SGDER.IDRE, SGDER.PCRE1, and SGDER.PCRE0
The transfer size of 3 bytes is regarded as 4 bytes.
3.4.3.
Transfer Byte Position in the DMA Transfer Intermediate Register
(SGDMAR)
The DMA transfer byte position in the "DMA Transfer Intermediate Register (SGDMAR)" depends on the
setting of the "DMA Transfer Update Enable Register (SGDER)" and the DMA transfer size.
If the size of a DMA transfer is less than 4 bytes, the byte position of DMA transfer is left-aligned.
The table below shows the relations between
"the setting of the DMA Transfer Update Enable Register (SGDER)"
and
"the byte position in the DMA Transfer Intermediate Register (SGDMAR)".
The byte position in the DMA Transfer Intermediate Register (SGDMAR) corresponds to the selection of
the following registers.
-
Amplitude Data Register (SGAR [15:0])
-
Frequency Data Register (SGFR [7:0])
-
Tone Output Number Register (SGNR [7:0])
The transfer size #1 is calculated by the setting of {SGDER.ARE1, SGDER.ARE0, SGDER.FRE, and
SGDER.NRE} in the "DMA Transfer Update Enable Register (SGDER)". When this transfer size #1 is not
4 bytes, the transfer byte position is left-aligned.
Summary of Contents for S6J3200 Series
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