CHAPTER 26:PCMPWM
982
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
At begin of operation when the PCMPWM is enabled, the module is in silence mode until the required
number of FIFO entries are written. This prevents possible FIFO under-runs directly after the start of
operation.
2.3.
Output Configuration
The two output channels of the PCMPWM module may be individually enabled and disabled. In addition,
the output polarity of each channel may be selected. The enable bits are PCMPWMi_OCTRL:EN0 and
PCMPWMi_OCTRL:EN1. The output polarity is programmed with PCMPWMi_OCTRL:LEVL0 and
PCMPWMi_OCTRL:LEVL1.
If a channel's output is disabled, all the corresponding signals stay at their inactive values. The inactive
value depends on the programmed output polarity. If a channel is programmed to an operation mode
which does not use all outputs, the unused outputs also stay at their inactive values. Table 2-1 shows the
inactive values of all outputs depending on the selected polarity.
Table 2-1 Inactive Output Values
PCMPWMi_OCTRL:LEVL0/LEVL1
PCMPWM_i_AH/BH
PCMPWM_i_AL/BL
0
1
0
1
0
1
Summary of Contents for S6J3200 Series
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