Cypress S6J3200 Series, Manual

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CHAPTER 25:Programmable CRC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 963
Table 3-1 Preliminary Input Data Bit-wise and/or Byte-wise Reflection/Swapping
RIBYT RIBIT SZ
Final Input Data for CRC Engine
+3 +2 +1 +0
0
0
00 XXXX XXXX XXXX XXXX XXXX XXXX D7------- D0
01 XXXX XXXX XXXX XXXX C7--------C0 D7--------D0
10 XXXX XXXX B7--------B0 C7--------C0 D7--------D0
11 A7--------A0 B7--------B0 C7--------C0 D7--------D0
1
00 XXXX XXXX XXXX XXXX XXXX XXXX D0--------D7
01 XXXX XXXX XXXX XXXX C0--------C7 D0--------D7
10 XXXX XXXX B0--------B7 C0--------C7 D0--------D7
11 A0---------A7 B0--------B7 C0--------C7 D0--------D7
1
0
00 XXXX XXXX XXXX XXXX XXXX XXXX D7--------D0
01 XXXX XXXX XXXX XXXX D7--------D0 C7--------C0
10 XXXX XXXX D7--------D0 C7--------C0 B7--------B0
11 D7---------D0 C7--------C0 B7--------B0 A7--------A0
1
00 XXXX XXXX XXXX XXXX XXXX XXXX D0--------D7
01 XXXX XXXX XXXX XXXX D0--------D7 C0--------C7
10 XXXX XXXX D0--------D7 C0--------C7 B0--------B7
11 D0---------D7 C0--------C7 B0--------B7 A0--------A7
3. The "preliminary input data" after applying the settings of CRCn_CFG:RIBIT/RIBYT results in the "final
input data", which is sent to the CRC engine for checksum calculation.
4. The CRCn_SEED register provides the initial value to the CRC engine. The required polynomial is
provided by CRCn_POLY register. The CRC engine starts its operation once CRCn_WR register is
written with the input data.
5. CRC engine performance: The performance of CRC engine for CRC checksum calculation is based on
the input data size and number of clock cycles (bus clock) required to complete a calculation. The
shows number of clock cycles required to get final checksum at CRCn_RD register with respect to input
data size.
Table 3-2 Clock Cycles Requirement for Checksum Calculation
Input Data Size Number of Clock Cycles Required for Final Checksum at CRCn_RD
8-bit Input data size (8-bit) + 2 = 10 clock cycles.
16-bit Input data size (16-bit) + 2 = 18 clock cycles.
24-bit Input data size (24-bit) + 2 = 26 clock cycles.
32-bit Input data size (32-bit) + 2 = 34 clock cycles.
6. The "preliminary checksum #1" bytes can be swapped/reflected bit-wise using CRCn_CFG:ROBIT
and/or byte-wise using CRCn_CFG:ROBYT. shows at which positions the checksum bits of
"preliminary checksum #1" S[(LEN-1):0] will be located in "preliminary checksum #2" after
CRCn_CFG:ROBIT/ROBYT settings have been applied. Only some examples of different
CRCn_CFG:LEN configurations are shown.
Note:
−
Only some examples for CRCn_CFG:LEN are shown.