Cypress S6J3200 Series, Manual

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CHAPTER 22:Media Local Bus Interface (MediaLB)
852 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.7.
MediaLBn Asynchronous Base Address Configuration Register
(MLBn_ABCR)
MediaLBn Asynchronous Base Address Configuration Register (MLBn_ABCR) defines the base address
for asynchronous receive/transmit system memory buffers.
REGISTER_NAME YOURPERIn_CSRi
OFFSET 0 + i*4
ACCESS_SIZE B H W
MULTIPLE 0:15
NUMERIC_TYPE
OTHER
MediaLB Asynchronous Base Address Configuration Register (MLBn_ABCR)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME ARBA[15] ARBA[14] ARBA[13] ARBA[12] ARBA[11] ARBA[10] ARBA[9] ARBA[8]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME ARBA[7] ARBA[6] ARBA[5] ARBA[4] ARBA[3] ARBA[2] ARBA[1] ARBA[0]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME ATBA[15] ATBA[14] ATBA[13] ATBA[12] ATBA[11] ATBA[10] ATBA[9] ATBA[8]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME ATBA[7] ATBA[6] ATBA[5] ATBA[4] ATBA[3] ATBA[2] ATBA[1] ATBA[0]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:16] ARBA[15:0] : Upper Half of Asynchronous Receive Base Address for DMA
mode
These bits allow system software to define the base address (ARBA[31:16]) for asynchronous receive
system memory buffers.
This base address is shared by all asynchronous receive channels and defines the upper 16 bits of the
32-bit system bus address for these channels.
This bit field is only used in DMA mode. In IO mode these bits are not used.