Cypress S6J3200 Series, Manual

Page: 331 / 1355

CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
330 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
5.15.
Pulse Counter Interrupt Enable Registers (ADC12Bn_PCIRQE0 to
1)
These registers contain enable bits for all 64 logical channels, dedicated to the generation of pulse
counter interrupt.
REGISTER_NAME ADC12Bn_PCIRQEi (i = 0 to 1)
OFFSET i*4
ACCESS_SIZE B H W
MULTIPLE 0:1
NUMERIC_TYPE
-
OTHER
-
5.15.1.
Pulse Counter Interrupt Enable Register (ADC12Bn_PCIRQE0)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME PCIRQE31 PCIRQE30 PCIRQE29 PCIRQE28 PCIRQE27 PCIRQE26 PCIRQE25 PCIRQE24
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME PCIRQE23 PCIRQE22 PCIRQE21 PCIRQE20 PCIRQE19 PCIRQE18 PCIRQE17 PCIRQE16
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME PCIRQE15 PCIRQE14 PCIRQE13 PCIRQE12 PCIRQE11 PCIRQE10 PCIRQE9 PCIRQE8
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME PCIRQE7 PCIRQE6 PCIRQE5 PCIRQE4 PCIRQE3 PCIRQE2 PCIRQE1 PCIRQE0
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:0] PCIRQE31 to 0 : Pulse Counter Interrupt Enable bits
Bit Description
0 Pulse counter interrupt is disabled.
1 Pulse counter interrupt is enabled.
Pulse counter interrupt is issued when this bit is "1" and the corresponding interrupt flags
ADC12Bn_PCIRQ0.PCIRQ31 to 0 and ADC12Bn_CHSTAT0 to 31.PCIRQ are set to "1".