Cypress S6J3200 Series, Manual

Page: 1329 / 1355

CHAPTER 37:Major Changes
1328 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Summary
E
rror
P
age
Error
C
orre
ct
P
age
Correct ID
Revision B
description
27
Notes:
,,,
- SCL4, 10, 12 and SDA4, 10, 12 of I2C is
not supported yet, and will be enhanced
after Revision B.
32
Notes:
,,,
- Multi-function serial interface of the
function digit 3, 4, 5, 6, 7, and 8 support
SCL4, 10, 12 and SDA4, 10, 12 of I2C
after Revision D.
#349
Note for Basic
Option
27 Notes;- ,,, 32
Notes;- ,,,
−
The CLK_CPU is assigned
for CPU clock. The CLK_CD3A0 is
assigned for Graphic clock. They are
defined at the chapter of Clock
Configuration.
#194
CHIP ID
information
28 - 33
Function digit: A, B, C, D
Revision B:
Chip ID: 0x10110000
JTAG ID: 0x100095CF
#140
Chip ID 28 Revision:B, Chip ID:0x10100010 33
Revision:B, Chip ID:-
Revision:C and D, Chip ID:0x10100100
#278
TEQFP256
support
30
Notes:
- ,,,
35
TEQFP256
Notes:
- ,,,
- TEQFP-256 is a package option under
planning.
#273
CR oscillation
stabilization
time
33 - 39
Embedded CR oscillation
See the platform manual in detail.
Stabilization time is as followings.
−
5us for 4MHz (Fast clock)
−
20us for 100kHz (Slow clock)
#259
Main clock
frequency
33
Main and sub oscillator is available.
- A wide range of 3.6 - 4MHz is available
for main oscillator
39
Main and sub oscillator is available.
−
A wide range of 3.6 - 16MHz is
available for main oscillator
#311
Power
domain reset
33 - 39
Power domain (PD):
----
See the platform manual and chapter
STATE TRANSITION in detail.
The product series supports the power off
control of PD1, PD2 (including PD3 and
5), and PD6.
The power domain resets of PD3 and
PD5 included in PD2 are not supported in
the product series, and "0" is always read
from the reset factor flags of them.
#175