Cypress S6J3200 Series, Manual

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CHAPTER 26:PCMPWM
994 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.2.
PCMPWM Output Control Register (PCMPWMi_OCTRL)
This Output Control Register is used to configure the individual output channels of the PCMPWM module.
REGISTER_NAME PCMPWMi_OCTRL
OFFSET 0x00000004
ACCESS_SIZE B, H, W
MULTIPLE 0
NUMERIC_TYPE
-
OTHER
-
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME Reserved LEVL1 LEVL0
ACCESS_TYPE R0,WX R/W R/W
PROT_TYPE Wp
INITIAL_VALUE 0 1 1
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME Reserved EN1 EN0
ACCESS_TYPE R0,WX R/W R/W
PROT_TYPE Wp
INITIAL_VALUE 0 0 0
[bit17] LEVL1 : Output Level Select Channel #1
This bit selects the output polarity of channel #1.
Bit Description
0 PCMPWM_1_AH/BH are low-active and PCMPWM_1_AL/BL are high-active
1 PCMPWM_1_AH/BH are high-active and PCMPWM_1_AL/BL are low-active