CHAPTER 18:Sound Generator
438
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Notes:
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The DMAC must finish the sequence from step 5 to 6, within the following time.
The limit time = (Frequency Data Register [SGFR] + 1) x 1 PWM cycle
−
The DMA transfer error means the occurrence of delay in the sound data setting. It causes
unsteady sound output. In that case, please fix the priority of DMA transfer in the system to finish
all data transfer within the limit time.
Summary of Contents for S6J3200 Series
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