Cypress S6J3200 Series, Manual

Page: 316 / 1355

CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 315
5.9.
Group Interrupted Interrupt Enable Registers (ADC12Bn_GRPIRQE0 to 1)
These registers contain enable bits for all 64 logical channels, dedicated to the generation of group
interrupted interrupt.
REGISTER_NAME ADC12Bn_GRPIRQEi (i = 0 to 1)
OFFSET i*4
ACCESS_SIZE B H W
MULTIPLE 0:1
NUMERIC_TYPE
-
OTHER
-
5.9.1.
Group Interrupted Interrupt Enable Register
(ADC12Bn_GRPIRQE0)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME GRPIRQE31 GRPIRQE30 GRPIRQE29 GRPIRQE28 GRPIRQE27 GRPIRQE26 GRPIRQE25 GRPIRQE24
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME GRPIRQE23 GRPIRQE22 GRPIRQE21 GRPIRQE20 GRPIRQE19 GRPIRQE18 GRPIRQE17 GRPIRQE16
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME GRPIRQE15 GRPIRQE14 GRPIRQE13 GRPIRQE12 GRPIRQE11 GRPIRQE10 GRPIRQE9 GRPIRQE8
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME GRPIRQE7 GRPIRQE6 GRPIRQE5 GRPIRQE4 GRPIRQE3 GRPIRQE2 GRPIRQE1 GRPIRQE0
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:0] GRPIRQE31 to 0 : Group Interrupted Interrupt Enable bits
Bit Description
0 Group interrupted interrupt disabled.
1 Group interrupted interrupt enabled.
Group interrupted interrupt is issued when this bit is "1" and the corresponding interrupt flags
(ADC12Bn_GRPIRQ0.GRPIRQ31 to 0 and ADC12Bn_CHSTAT0 to 31.GRPIRQ) are set to "1".