Revision History
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
1351
Revision
ECN No.
Description of Change
CHAPTER 23: Stereo Audio DAC 1. Overview
[Improve] Added the description for the reference information
CHAPTER 23: Stereo Audio DAC 4.4. DAC Control Register(DACTRL)
[Improve] Added the note for the description of FEST[4:0] and DMAEN bits
CHAPTER 24: Inter-IC Sound (I2S)
[Improve] remove unique clock name (CLK_HAPPS1B0)
CHAPTER 24: Inter-IC Sound (I2S) 1. Overview
[Improve] Added the description for the reference information
CHAPTER 24:Inter-IC Sound (I2S) 4. Registers
[Improve] Added ACCESS_SIZE on "Memory Layout of I2S Registers".
CHAPTER 24: Inter-IC Sound (I2S) 4.9. Interrupt Control Register (I2Sn_INTCNT)
[Improve] Added the note for description of TFTH and RFTH bits
CHAPTER 25:Programmable CRC 4. Registers
[Improve] Added ACCESS_SIZE on Figure 4-1 Memory Layout of Programmable CRC Registers.
CHAPTER 25: Programmable CRC 4.3. CRC Final XOR Register (CRCn_FXOR)
[Improve] Added bit name to 30 bit in the register table
[Improve] Delete "[31:0]" from the explanation of FXOR
CHAPTER 26: PCMPWM 1. Overview
[Improve] Added the description for the reference information
CHAPTER 26: PCMPWM 4.1. PCMPWM Control Register (PCMPWMi_CONTROL)
[Improve] [Improve] Added the note for description of FEST[4:0] bits
CHAPTER 28: LCD Controller 6.3. LCDC Control Register 1: LCR1
[Improve] Added the description of LCR1 configuration for not using LCDC
CHAPTER 28: LCD Controller 6.4. Common Pin Switching Register: LCDCMR
[Improve] Added the description of LCDCMR configuration for not using LCDC
CHAPTER 30:FPD-Link Converter 2. Configuration and Block Diagram
[Improve] Change in Figure 2-1.
[Improve] Change 'Notes'.
CHAPTER 30:FPD-Link Converter Table 2 1: FPD-Link Port Definition
[Enhance] Change TXCLK/TXCLKP/TXCLKM to TXIN4[6:0]/TXOUT4P/TXOUT4M and add NOTE.
CHAPTER 30:FPD-Link Converter 3.4. Power ON/Power DOWN Sequence
[Enhance] Add power on and power down sequence.
CHAPTER 30: FPD-Link Converter 4.3. Control1 Registers (CTRL1)
[Improve] Modify description of the LFCTRL, VCSEL and VDSEL.
CHAPTER 30:FPD-Link Converter 4.3. Control1 Registers (CTRL1)
[Improve] Change the Reserved[29:28] to the LFTCTRL[29:28] of the CTR1 Register
[Improve] Change the Reserved[7:6] to the FRANGE[7:6] of the CTR1 Register
[Improve] Delete each value of MIN and MAX in the VCSEL.
[Improve] Delete each value of MIN and MAX in the VDSEL.
CHAPTER 33: Graphics Subsystem 4. Registers
[Improve] Corrected bit width in 4.2.1.3 IPIdentifier ([bit7:3] -> [bit7:4]
[Improve] Corrected name of bit [2] in 4.2.1.6 VRamInterruptPreset
[Improve] Corrected name of bit [2] in 4.2.1.7 VRamInterruptClear
[Improve] Corrected name of bit [2] in 4.2.1.8 VRamInterruptStatus
Summary of Contents for S6J3200 Series
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