Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 607
−
A pause opcode of 0001
h
−
A pause quantum register
−
Fill of 00
h
to take the frame to minimum frame length
−
Valid FCS
The pause quantum used in the generated frame will depend on the trigger source for the frame as
follows:
−
If bit 11 is written with “1”, the pause quantum will be taken from the Transmit Pause Quantum
register. The Transmit Pause Quantum register resets to a value of 0xFFFF giving maximum pause
quantum as initial value.
−
If bit 12 is written with “1”, the pause quantum will be zero.
After transmission, a pause frame transmitted interrupt will be generated (bit 14 of the Interrupt Status
register) and the only statistics register that will be incremented will be the Pause Frames Transmitted
register.
Pause frames can also be transmitted by the MAC using normal frame transmission methods.
3.8.
MAC PFC Based Pause Frame Support
The Ethernet MAC supports PFC Priority Based Pause transmission and reception. Before PFC pause
frames can be received, bit 16 of the Network Control register must be set to “1”.
Note: Refer to IEEE Std 802.1Qbb for a full description of priority based pause operation.
The start of a PFC pause frame looks like this:
Destination
Address
Source
Address
Type
(MAC Control Frame)
Pause
Opcode
Priority
Enable Vector
Pause Time
0180C2000001
h
6 bytes 8808
h
0101
h
2 bytes 2 bytes
3.8.1.
PFC Pause Frame Reception
The ability to receive and decode priority based pause frames is enabled by setting bit 16 of the Network
Control register. When this bit is set, the Ethernet MAC will match either classic IEEE Std 802.3 pause
frames or PFC priority based pause frames. Once a priority based pause frame has been received and
matched, then from that moment on the Ethernet MAC will only match on priority based pause frames
(this is IEEE Std 802.1Qbb requirement, known as PFC negotiation). Once priority based pause has been
negotiated, any received IEEE Std 802.3x format pause frames will not be acted upon.
If a valid priority based pause frame is received then the Ethernet MAC will decode the frame and
determine which, if any, of the 8 priorities require to be paused. Up to 8 pause time registers are then
updated with the 8 pause times extracted from the frame regardless of whether a previous pause
operation is active or not. An interrupt (either bit 12 or bit 13 of the Interrupt Status register) is triggered
when a pause frame is received, but only if the interrupt has been enabled. Pause frames received with
non-zero quanta are indicated through the interrupt bit 12 of the Interrupt Status register. Pause frames
received with zero quanta are indicated on bit 13 of the Interrupt Status register. The loading of a new
pause time occurs since the Ethernet MAC is operating in full duplex mode. A valid pause frame is
defined as having a destination address that matches either the address stored in Specific Address 1
register of if it matches the reserved address of 0180C2000001
h
. It must also have the MAC control fram
Type ID of 8808
h
and have the pause opcode 0101
h
.
Pause frames that have FCS or other errors will be treated as invalid and will be discarded. Valid pause
frames received will increment the Pause Frames Received statistic register.