CHAPTER 21:Ethernet MAC
642
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.9.
Interrupt Status Register (ETHERNETn_int_status)
Description of Interrupt Status register is shown. If not configured for priority queuing, the Ethernet MAC
generates a single interrupt. This register indicates the source of this interrupt. The corresponding bit in
the Interrupt Mask register must be clear for a bit to be set. If any bit is set in this register the interrupt
signal will be asserted. For test purposes each bit can be set or reset by writing to the Interrupt Mask
register. The default configuration is shown below whereby every bit is reset to “0” on writing a "1" to the
appropriate bit. Reading has no effect on the status of the bit.
REGISTER_NAME
ETHERNETn_int_status
OFFSET
0x024
ACCESS_SIZE
W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET
31
30
29
28
27
26
25
24
BIT_NAME
Reserved
tsu_timer_c
omparison_i
nterrupt
Reserved
receive_lpi_
indication_s
tatus_bit_ch
ange
tsu_second
s_register_i
ncrement
ptp_pdelay_
resp_frame
_transmitte
d
ptp_pdelay_
req_frame_t
ransmitted
ACCESS_TYPE
R0,WX
R,W1C
R,WX
R,W1C
R,W1C
R,W1C
R,W1C
PROT_TYPE
Wp
INITIAL_VALUE
0
0
0
0
0
0
0
BIT_OFFSET
23
22
21
20
19
18
17
16
BIT_NAME
ptp_pdelay_
resp_frame
_received
ptp_pdelay_
req_frame_r
eceived
ptp_sync_fr
ame_trans
mitted
ptp_delay_r
eq_frame_tr
ansmitted
ptp_sync_fr
ame_receiv
ed
ptp_delay_r
eq_frame_r
eceived
Reserved
ACCESS_TYPE
R,W1C
R,W1C
R,W1C
R,W1C
R,W1C
R,W1C
R,WX
PROT_TYPE
Wp
INITIAL_VALUE
0
0
0
0
0
0
0x0
BIT_OFFSET
15
14
13
12
11
10
9
8
BIT_NAME
Reserved
pause_fram
e_transmitt
ed
pause_time
_elapsed
pause_fram
e_with_non
_zero_paus
e_quantum
_received
resp_not_o
k
receive_ove
rrun
Reserved
ACCESS_TYPE
R,WX
R,W1C
R,W1C
R,W1C
R,W1C
R,W1C
R,WX
PROT_TYPE
Wp
INITIAL_VALUE
0
0
0
0
0
0
0x0
BIT_OFFSET
7
6
5
4
3
2
1
0
Summary of Contents for S6J3200 Series
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