Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 653
4.12.
Interrupt Mask Register (ETHERNETn_int_mask)
The Interrupt Mask register is a read only register indicating which interrupts are masked. All bits are set
at reset and can be reset individually by writing to the Interrupt Enable register or set individually by
writing to the Interrupt Disable register. Having separate address locations for enable and disable saves
the need for performing a read modify write when updating the Interrupt Mask register. For test purposes
there is a write-only function to this register that allows the bits in the Interrupt Status register to be set or
cleared, regardless of the state of the Interrupt Mask register.
REGISTER_NAME ETHERNETn_int_mask
OFFSET 0x030
ACCESS_SIZE W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved
tsu_timer_c
omparison_
mask
wol_event_r
eceived_ma
sk
rx_lpi_indic
ation_mask
tsu_second
s_register_i
ncrement_
mask
ptp_pdelay_
resp_frame
_transmitte
d_mask
ptp_pdelay_
req_frame_t
ransmitted_
mask
ACCESS_TYPE R0,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x0 1 1 1 1 1 1
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME
ptp_pdelay_
resp_frame
_received_
mask
ptp_pdelay_
req_frame_r
eceived_ma
sk
ptp_sync_fr
ame_trans
mitted_mas
k
ptp_delay_r
eq_frame_tr
ansmitted_
mask
ptp_sync_fr
ame_receiv
ed_mask
ptp_delay_r
eq_frame_r
eceived_ma
sk
pcs_link_pa
rtner_page_
mask
pcs_auto_n
egotiation_c
omplete_int
errupt_mas
k
ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R,WX
PROT_TYPE Wp
INITIAL_VALUE 1 1 1 1 1 1 1 1
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME
external_int
errupt_mas
k
pause_fram
e_transmitt
ed_interrupt
_mask
pause_time
_zero_interr
upt_mask
pause_fram
e_with_non
_zero_paus
e_quantum
_interrupt_
mask
resp_not_o
k_interrupt_
mask
receive_ove
rrun_interru
pt_mask
link_change
_interrupt_
mask
not_used
ACCESS_TYPE R,WX R,WX R,WX R,WX R,WX R,WX R,WX R1, WX
PROT_TYPE Wp
INITIAL_VALUE 1 1 1 1 1 1 1 1