Cypress S6J3200 Series, Manual

Page: 340 / 1355

CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 339
5.18.
A/D Channel Trigger Clear Registers (ADC12Bn_TRGCL0 to 1)
These registers contain bits for clearing corresponding A/D channel trigger status flags in the
ADC12Bn_TRGST0 to 1 registers. The 64 bits are assigned to 64 logical channels.
REGISTER_NAME ADC12Bn_TRGCLi (i = 0 to 1)
OFFSET i*4
ACCESS_SIZE B H W
MULTIPLE 0:1
NUMERIC_TYPE
-
OTHER
-
5.18.1.
A/D Channel Trigger Clear Register (ADC12Bn_TRGCL0)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME TRGCL31 TRGCL30 TRGCL29 TRGCL28 TRGCL27 TRGCL26 TRGCL25 TRGCL24
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME TRGCL23 TRGCL22 TRGCL21 TRGCL20 TRGCL19 TRGCL18 TRGCL17 TRGCL16
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME TRGCL15 TRGCL14 TRGCL13 TRGCL12 TRGCL11 TRGCL10 TRGCL9 TRGCL8
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME TRGCL7 TRGCL6 TRGCL5 TRGCL4 TRGCL3 TRGCL2 TRGCL1 TRGCL0
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:0] TRGCL31 to 0 : Trigger Status Clear bits
Bit Description
0 No effect.
1 A/D channel trigger status is cleared.
When this bit is set to "1", the corresponding bit in the ADC12Bn_TRGST0 register and TRGST bit in
the corresponding ADC12Bn_CHSTAT0 to 31 register are cleared.