Cypress S6J3200 Series, Manual

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Table of Contents
10 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
5. Appendix ............................................................................................................................ 564
5.1. Gain for Volume Control ....................................................................................... 564
5.2. Fade In/Fade Out Time ......................................................................................... 571
5.3. Digital Filter .......................................................................................................... 572
CHAPTER 21: Ethernet MAC ............................................................................................................ 575
1. Overview ............................................................................................................................ 576
2. Configuration and Block Diagram ....................................................................................... 578
3. Operation of the Ethernet MAC .......................................................................................... 579
3.1. Direct Memory Access Interface ........................................................................... 579
3.2. MAC Transmitter Block ......................................................................................... 594
3.3. MAC Receiver Block ............................................................................................. 595
3.4. Checksum Offload for IP, TCP, and UDP .............................................................. 595
3.5. MAC Filtering Block .............................................................................................. 597
3.6. IEEE Std 1588 and IEEE Std 802.1AS Support ................................................... 600
3.7. MAC IEEE Std 802.3 Pause Frame Support ........................................................ 605
3.8. MAC PFC Based Pause Frame Support .............................................................. 607
3.9. Energy Efficient Ethernet Support ........................................................................ 609
3.10. LPI Operation in Ethernet MAC ............................................................................ 609
3.11. IEEE Std 802.1Qav Support – Credit Based Shaping .......................................... 610
3.12. PHY Interface ....................................................................................................... 610
3.13. Jumbo Frames...................................................................................................... 610
4. Registers ............................................................................................................................ 611
4.1. Network Control Register (ETHERNETn_network_control) .................................. 619
4.2. Network Configuration Register (ETHERNETn_network_configuration) .............. 623
4.3. Network StatusNetwork Status Register (ETHERNETn_network_status) ............ 628
4.4. DMA Configuration Register (ETHERNETn_dma_config) .................................... 630
4.5. Transmit Status Register (ETHERNETn_transmit_status) ................................... 634
4.6. RX Buffer Queue Base Address Register (ETHERNETn_receive_q_ptr) ............. 636
4.7. TX Buffer Queue Base Address Register (ETHERNETn_transmit_q_ptr) ............ 638
4.8. Receive Status Register (ETHERNETn_receive_status) ..................................... 640
4.9. Interrupt Status Register (ETHERNETn_int_status) ............................................. 642
4.10. Interrupt Enable Register (ETHERNETn_int_enable)........................................... 647
4.11. Interrupt Disable Register (ETHERNETn_int_disable) ......................................... 650
4.12. Interrupt Mask Register (ETHERNETn_int_mask) ............................................... 653
4.13. PHY Maintenance Register (ETHERNETn_phy_management) ........................... 660
4.14. Receive Pause Quantum Register (ETHERNETn_pause_time) .......................... 662
4.15. Transmit Pause Quantum Register (ETHERNETn_tx_pause_quantum).............. 663
4.16. TX Partial Store and Forward Register (ETHERNETn_pbuf_txcutthru) ................ 664
4.17. RX Partial Store and Forward Register (ETHERNETn_pbuf_rxcutthru) ............... 666
4.18. Jumbo-Frame Maximum Length Register (ETHERNETn_jumbo_max_length) .... 668
4.19. AXI Maximum Pipeline Register (ETHERNETn_axi_max_pipeline) ..................... 669
4.20. Hash Bottom Register (ETHERNETn_hash_bottom) ........................................... 671
4.21. Hash Top Register (ETHERNETn_hash_top) ....................................................... 672
4.22. Specific Address Bottom i Register (ETHERNETn_spec_add_bottom_i) (i=1 to 4)
.............................................................................................................................
673
4.23. Specific Address Top i Register (ETHERNETn_spec_add_top_i) (i=1 to 4) ......... 674
4.24. Type ID Match i Register (ETHERNETn_spec_type_i) (i= 1 to 4) ........................ 676
4.25. IPG Stretch Register (ETHERNETn_stretch_ratio) .............................................. 677