Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 597
not be recognized). If the frame data already had the FCS field, this would be corrupted by the
substitution of the new checksum fields.
If these conditions are met, the transmit checksum offload engine will calculate the IP, TCP, and UDP
checksums as appropriate. Once the full packet is completely written into TX Packet Buffer Memory, the
checksums will be valid and the relevant memory locations will be updated for the new checksum fields
as per standard IP/TCP and UDP packet structures.
If the transmitter checksum engine is prevented from generating the relevant checksums, bits [22:20] of
the
Transmit Buffer Descriptor Entry will be updated to identify the reason for the error. Note that the
frame will still be transmitted but without the checksum substitution, as typically the reason that the
substitution did not occur was that the protocol was not recognized.
3.5.
MAC Filtering Block
The filter block determines which frames should be written to the External FIFO Interface and on to the
Ethernet MAC DMA.
Whether a frame is passed depends on what is enabled in the Network Configuration register, the
contents of the Specific Address, Type ID Match and Hash registers and the frame’s destination address
and type field.
Ethernet frames are transmitted a byte at a time, least significant bit first. The first six bytes of an Ethernet
frame make up the destination address. The first bit of the destination address, which is the LSB of the
first byte of the frame, is the group or individual bit. This is “1” for multicast addresses and “0” for unicast
ones. The “all ones” address is the broadcast address and a special case of multicast.
The Ethernet MAC supports recognition of specific source or destination addresses. The number of
specific source or destination address filters is four. Each specific address filter consists of two registers,
Specific Address Bottom i register and Specific Address Top i register. Specific Address Bottom i register
stores the first four bytes of the compares source or destination address. Specific Address Top i register
contains the last two bytes of this address, a control bit to select between source or destination address
filtering and a 6-bit byte mask field to allow masking certain bytes during the comparison. The first filter
(Filter 1) is slightly different to all other filters in that there is no byte mask. Instead address comparison
against individual bits of Specific Address 1 register can be masked using the unique Specific Address
Mask 1 register. The addresses stored in all filters can be specific (unicast), group (multicast), local or
universal.
The destination or source address of received frames is compared against the data stored in the Specific
Address registers once they have been activated. The addresses are deactivated at reset or when their
corresponding Specific Address Bottom i register is written. They are activated when the corresponding
Specific Address Top i register is written. If a receive frame address matches an active address, the frame
is written to the External FIFO Interface and on to DMA memory if used.
Frames may be filtered using the Type ID field for matching. Four Type ID Match registers exist and each
can be enabled for matching by writing a “1” to the MSB (bit 31) of the respective register. When a frame
is received, the matching is implemented as an OR function of the various types of match.
The content of each Type ID register (when enabled) is compared against the length/Type ID of the frame
being received (e.g. bytes 13 and 14 in non-VLAN and non-SNAP encapsulated frames) and copied to
system memory if a match is found. The encoded Type ID match bits (Word 0, bit 22 and bit 23) in the
receive buffer descriptor status are set indication which Type ID Match register generated the match, if
the receive checksum offload is disabled.