Cypress S6J3200 Series, Manual

Page: 655 / 1355

CHAPTER 21:Ethernet MAC
654 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME
transmit_co
mplete_inte
rrupt_mask
amba_error
_interrupt_
mask
retry_limit_e
xceeded_or
_late_collisi
on_mask
transmit_bu
ffer_under_r
un_interrupt
_mask
transmit_us
ed_bit_read
_interrupt_
mask
receive_use
d_bit_read_
interrupt_m
ask
receive_co
mplete_inte
rrupt_mask
manageme
nt_done_int
errupt_mas
k
ACCESS_TYPE R,WX R,WX R,WX R1,WX R,WX R,WX R,WX R,WX
PROT_TYPE Wp
INITIAL_VALUE 1 1 1 1 1 1 1 1
[bit31:30] Reserved
Always read "0". Writing has no effect.
[bit29] tsu_timer_comparison_mask
Enable TSU timer comparison interrupt mask.
[bit28] wol_event_received_mask
A read of this register returns the value of the WOL event received mask. A write to this register directly
affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be
generated if a 1 is written.
Bit Description
0 Interrupt is enabled.
1 Interrupt is disabled.
[bit27] rx_lpi_indication_mask
A read of this register returns the value of the RX LPI indication mask. A write to this register directly
affects the state of the corresponding bit in the interrupt status register, causing an interrupt to be
generated if a 1 is written
Bit Description
0 Interrupt is enabled.
1 Interrupt is disabled.
[bit26] tsu_seconds_register_increment_mask: IEEE 1588 Timer Seconds register
increment mask
A read of this register returns the value of the IEEE 1588 Timer Seconds register increment mask. A
write to this register directly affects the state of the corresponding bit in the Interrupt Status register,
causing an interrupt to be generated if a "1" is written.
Bit Description
0 Interrupt is enabled.
1 Interrupt is disabled.
[bit25] ptp_pdelay_resp_frame_transmitted_mask: PTP Pdelay_Resp frame transmitted
mask
A read of this register returns the value of the PTP Pdelay_Resp frame transmitted mask. A write to this
register directly affects the state of the corresponding bit in the Interrupt Status register, causing an
interrupt to be generated if a "1" is written.