Cypress S6J3200 Series, Manual

Page: 1342 / 1355

CHAPTER 37:Major Changes
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1341
Summary
E
rror
P
age
Error
C
orre
ct
P
age
Correct ID
TYPO in bit
name of
ETHERNET
register
647,
650
(bit25:disable_ptp_pdelay_reso_frame_tr
ansmitted)
(bit25:ptp_pdelay_reso_frame_transmitte
d)
647,
650
(bit25:disable_ptp_pdelay_resp_frame_tr
ansmitted)
(bit25:ptp_pdelay_resp_frame_transmitte
d_mask)
#422
Ethernet
Description
680
(4.33 IEEE 1588 Timer Comparison Value
Seconds Bottom Register
(ETHERNETn_tsu_sec_cmp)
- (Delete) #426
TYPO in bit
name of
ETHERNET
register
759 (bit27:20:rx_buffer_length) 758 (bit27:20:rx_buffer_length_def) #427
TYPO in bit
name of
ETHERNET
register
772
[bit5] retry_limit_exceeded: Retry limit
exceeded
771
[bit5]
retry_limit_exceeded_or_late_collision
: Retry limit exceeded
#419
TYPO in bit
name of
ETHERNET
register
792
[bit28] dstc_match_enable: DS/TC match
enable
[bit27:12] udp_port_match_enable: UDP
port match enable
[bit11:4] dstc_match_enable: DS/TC
match enable
791
[bit28] dstc_enable: DS/TC enable
[bit27:12] udp_port_match: UDP port
match
[bit11:4] dstc_match: DS/TC match
#424
TYPO in bit
name of
ETHERNET
register
795,
797,
799
-
794,
796,
798
(bit0:reserved) #425
TYPO in
offset address
of
ETHERNET
register
799 (OFFSET:(0x6E0 + (i*0x4) + ((i-1)*0x4))) 798 (OFFSET:(0x640 + ((i-1)*0x4))) #428
Link
information
for headline
6.8
1042 See 0, 6.9 1040 See 6.8, 6.9 #369
Indicator
interrupt via
Wakeup
Controller
1093 - 1091
3.5.3 Return from PSS Mode
An interrupt of indicator PWM can be
applied to a trigger of returning from PSS
mode. Then the bus clock CLK_SYSC0P
should be supplied during the PSS mode.
#435
Enhancement
of Graphic
subsystem
1177 - 1175 (Add another HyperBus interface) #405