Cypress S6J3200 Series, Manual

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CHAPTER 22:Media Local Bus Interface (MediaLB)
872 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
MLBn_CNBCRn.BSA[15:2] when the Next Buffer is ready for processing. This Current Buffer address
pointer, except when associated with isochronous channels, should always be quadlet aligned (i.e., set
BCA[1:0] to "00" for Synchronous, Asynchronous and Control channels). During the processing of the
Current Buffer, the BCA field marks which quadlet of the buffer is currently being processed. The upper
half of the beginning address of the Current Buffer is system memory is defined by MLBn_SBCR.SRBA,
MLBn_ABCR.ARBA, MLBn_CBCR.CRBA, or MLBn_IBCR.IRBA when MLBn_CECRn.TR is clear;
MLBn_SBCR.STBA, MLBn_ABCR.ATBA, MLBn_CBCR.CTBA, or MLBn_IBCR.ITBA when
MLBn_CECRn.TR is set, dependant on the value of MLBn_CECRn.CT[1:0].
In IO mode, this bit field defines the Receive Data Buffer bits - RDB[31:16].
This field contains the upper half of the next quadlet of receive data when the logical channel is
configured as receive channel.
[bit15:0] BFA[15:0] : Buffer Final Address
This bit field has different interpretations for DMA mode and IO mode.
In DMA mode, the BFA field defines a 16-bit address pointer, which identifies the lower half of the ending
address of the Current Buffer in system memory. The BFA[15:2] bits are loaded from
MLBn_CNBCRn.BEA[15:2] when the Next Buffer is read for processing. This Current Buffer address
pointer, except when associated with isochronous channels, should always be quadlet aligned (i.e.,
BFA[1:0] equals "00" for Synchronous, Asynchronous and Control channels). During the processing of
the Current Buffer, the point at which the BCA field becomes equal to (or greater than) the BFA field
indicates that the processing of the Current Buffer will end upon successful completion of the current
quadlet (for isochronous and synchronous channels) or upon successful completion of the current packet
(for asynchronous and control channels). It is the responsibility of system software to ensure the system
memory buffers (for RX asynchronous and control channels) can accommodate overflow in the size of the
largest packet supported. Additionally, single-packet buffering can be used by simply programming
MLBn_CNBCRn.BSA[15:2] = MLBn_CNBCRn.BEA[15:2].
The upper half of the ending address of the Current Buffer in system memory is defined by
MLBn_SBCR.SRBA, MLBn_ABCR.ARBA, MLBn_CBCR.CRBA, and MLBn_IBCR.IRBA when
MLBn_CECRn.TR is clear; MLBn_SBCR.STBA, MLBn_ABCR.ATBA, MLBn_CBCR.CTBA, or
MLBn_IBCR.ITBA when MLBn_CECRn.TR is set, dependant on the value of MLBn_CECRn.CT[1:0].
In IO mode, this bit field defines the Receive Data Buffer bits - RDB[15:0].
This field contains the lower half of the next quadlet of receive data when the logical channel is configured
as receive channel.