Cypress S6J3200 Series, Manual

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CHAPTER 29:Indicator PWM
1094 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
3.3.
Timer Count Operation Stop
A timer count stop is requested by setting the timer count enable bit (ICNTCR:CTEN) to 0 while a timer
count operation is in progress (ICNTCR:DOP=1). When the PWM timer stops the count, timer count
operation stop (ICNTCR:DOP=0) is indicated as the timer status. PWM output maintains the output status
as during timer count stop.
Figure 3-3: Timing Chart while Timer Count Operation is Stopped
4T+3TR
T: Main oscillator clock cycle
TR: Register clock cycle
CNTEN
Count clock
Count value
PWM output
waveform
0x0009
９９９
0x0007 0x0008 0x0006
DOP
0x000A
９９９
0x000B
９９９
A time of 4T+3TR (T: main oscillator clock cycle, TR: register clock) is required until the counter is
stopped (ICNTCR:DOP=0) after the CTEN bit becomes 0.
Figure 3-3 shows the interrupt factors and a timing chart for when the cycle setting value is 0xB and the
duty value is 0x9.