CHAPTER 24:Inter-IC Sound (I2S)
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
913
Reception Only Mode
Table 3-2 Reception Only Mode
Transfer Setting
Operation
Master Mode (I2Sn_CNTREG:MSMD = "1")
Slave Mode (I2Sn_CNTREG:MSMD = "0")
Reception
only
I2Sn_CNTREG:
TXDIS = "1"
I2Sn_CNTREG:
RXDIS = "0"
Start
Free-running mode
(I2Sn_CNTREG:FRUN = "1"):
Frame synchronous signal starts to output after
I2Sn_OPRREG:START bit becomes "1" and
I2Sn_OPRREG:RXENB bit is "1" when reception
FIFO is not full.
From the second time, frame synchronous signal
with the frame rate determined by the register
setting is output.
Burst mode
(I2Sn_CNTREG:FRUN = "0"):
When I2Sn_OPRREG:START bit is "1" and
I2Sn_OPRREG:RXENB bit is "1", frame
synchronous signal is output to receive frame if
reception FIFO is not full. If the FIFO is full, the
signal is not output.
Free-running mode
(I2Sn_CNTREG:FRUN = "1"):
When I2Sn_OPRREG:START bit is "1" and
I2Sn_OPRREG:RXENB bit is "1", input frame
synchronous signal with the frame rate
determined by the register setting. Frame should
be received every time the signal is input.
Burst mode (I2Sn_CNTREG:FRUN = "0"):
When I2Sn_OPRREG:START bit is "1" and
I2Sn_OPRREG:RXENB bit is "1", frame
reception is performed every time frame
synchronous signal is input. The signal is input
with less speed than the frame rate in the
free-running mode.
Stop
At the time of stop, frame is not imported from
serial bus even though reception FIFO is empty.
To maintain I2Sn_OPRREG:START bit to "1":
When "0" is written to I2Sn_OPRREG:RXENB,
reception FIFO becomes empty.
Although frame synchronous signal is kept
outputting in the free-running mode, frame is not
received. In the burst mode, frame is not received
and the signal is not output.
To make I2Sn_OPRREG:START bit "0":
When "0" is written to I2Sn_OPRREG:START,
reception FIFO becomes empty. Clock supply to
the serial control part stops regardless of
I2Sn_OPRREG:RXENB setting, and SCK supply
to the external part is stopped as well.
To maintain I2Sn_OPRREG:START bit to "1":
Reception FIFO becomes empty by writing "0" to
I2Sn_OPRREG:RXENB.
The input frame synchronous signal is ignored,
and frames are not received.
To make I2Sn_OPRREG:START bit "0":
When "0" is written to the
I2Sn_OPRREG:START bit, the reception FIFO
becomes empty. The input frame synchronous
signal is ignored regardless of
I2Sn_OPRREG:RXENB setting, and frames are
not received.
Abnormality
When writing to reception FIFO occurs while it is
full, I2Sn_STATUS:RXOVR is set to "1".
I2Sn_STATUS:RXUDR bit is set to "1" when read
access to reception FIFO occurs while it is empty.
When writing to reception FIFO occurs while it is
full, I2Sn_STATUS:RXOVR is set to "1". When
read access to reception FIFO occurs while it is
empty, I2Sn_STATUS:RXUDR is set to "1".
Free-running mode:
If frame synchronous signal is not input with the
frame rate defined by the register setting,
I2Sn_STATUS:FERR bit is set to "1".
Summary of Contents for S6J3200 Series
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