Cypress S6J3200 Series, Manual

Page: 333 / 1355

CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
332 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
5.16.
Pulse Counter Interrupt Clear Registers (ADC12Bn_PCIRQC0 to 1)
These registers contain bits for clearing corresponding pulse counter interrupt flags in the
ADC12Bn_PCIRQ0 to 1 registers. The 64 bits are assigned to 64 logical channels
REGISTER_NAME ADC12Bn_PCIRQCi (i = 0 to 1)
OFFSET i*4
ACCESS_SIZE B H W
MULTIPLE 0:1
NUMERIC_TYPE
-
OTHER
-
5.16.1.
Pulse Counter Interrupt Clear Register (ADC12Bn_PCIRQC0)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME PCIRQC31 PCIRQC30 PCIRQC29 PCIRQC28 PCIRQC27 PCIRQC26 PCIRQC25 PCIRQC24
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME PCIRQC23 PCIRQC22 PCIRQC21 PCIRQC20 PCIRQC19 PCIRQC18 PCIRQC17 PCIRQC16
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME PCIRQC15 PCIRQC14 PCIRQC13 PCIRQC12 PCIRQC11 PCIRQC10 PCIRQC9 PCIRQC8
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME PCIRQC7 PCIRQC6 PCIRQC5 PCIRQC4 PCIRQC3 PCIRQC2 PCIRQC1 PCIRQC0
ACCESS_TYPE R0,W R0,W R0,W R0,W R0,W R0,W R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:0] PCIRQC31 to 0 : ADC Pulse Counter Interrupt Clear bits
Bit Description
0 No effect.
1 Pulse counter interrupt cleared.
When this bit is set to "1", the corresponding bit in the ADC12Bn_PCIRQ0 register and PCIRQ bit in the
corresponding ADC12Bn_CHSTAT0 to 31 register are cleared.