Cypress S6J3200 Series, Manual

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CHAPTER 29:Indicator PWM
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1115
5.
Precautions for Using This Device
This section explains precautions during use.
5.1.
Notes to Observe When Accessing a Register

Status control register (ISTC) access
To clear a specific bit in this register, write "1" to the corresponding bit in the status control clear register
(ISTCC).
To set a specific bit in this register, write "1" to the corresponding bit in the status control set register
(ISTCS).
Data can be written directly to this register only when writing to all bits.
5.2.
Indicator PWM Operation Precautions

Precautions when configuring settings using a program
Timer control register (ITMCR) CKS2-0 bits, PWM cycle setting register (IPCSR), and PWM duty setting
register (IPDUT) settings are not reflected if they are configured while a count operation is in progress
(ICNTCR:DOP=1). Be sure to stop the count (ICNTCR:DOP=0) before configuring these settings.
If the interrupt request flag set timing and clear timing overlap, the flag set has priority, and the clear
operation is disabled.
If the load timing and count timing overlap, the load operation has priority for the down counter.
When consecutively setting STRG bits, allow a time of at least 8T (T: main clock cycle) between settings.
Failure to do so may result in a setting not being reflected.

Note that re-setting STRG bit during timer operation.
During PWM timer operation, the re-setting of the software trigger (ICNTCR:STRG="1") allows to
update the counter value. However, as a result of different between register clock speed and counter
clock(Main clock) speed, the count value of the counter at last time would reach the register value of
IPDUT or IPCSR before the re-setting of the software trigger is reflected in the counter. In this case, Note
that there is a possibility that the Duty match interrupt and Underflow interrupt is generated.