Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
594 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
The interrupt outputs from the Ethernet MAC match the number of supported priority queues. Only
Ethernet MAC DMA related events are reported using the individual interrupt outputs, as the Ethernet
MAC can relate these events to specific queues. All other events generated within the Ethernet MAC are
reported in the interrupt associated with the lowest priority queue (Queue 0). For the lowest priority queue
the Interrupt Status register is located at offset address 0x024. For all other priority queues, the Interrupt
Status register is located at sequential offset addresses starting at 0x400.
3.2.
MAC Transmitter Block
The MAC Transmitter operates in full duplex and transmits frames in accordance with the Ethernet IEEE
Std 802.3 standard.
A small input buffer receives data through the External FIFO Interface (from the Ethernet MAC DMA
module) which, depending on the data_bus_width control bits in the Network Configuration register, will
extract data in 64-bit form. All subsequent processing prior to the final output is performed in bytes.
Transmit data can be output using the MII Interface.
Frame assembly starts by adding preamble and the start frame delimiter (SFD). Data is taken from the
Transmit FIFO interface a word at a time. If necessary, padding is added to take the frame length to 60
bytes. CRC is calculated using an order 32 bit polynomial. This is inverted and appended to the end of the
frame taking the frame length to a minimum of 64 bytes. If the “No CRC” bit (bit 16) is set in the second
word (Word 1) of the last buffer descriptor of a transmit frame neither pad nor CRC are appended. The
“No CRC” bit can also be set through the FIFO interface.
In full duplex mode, frames are transmitted immediately. Back to back frames are transmitted at least 96
bit times apart to guarantee the Interpacket Gap.
If the collision signal is asserted during transmission, the transmitter will transmit a jam sequence of 32
bits taken from the data register and then retries transmission after the back off time has elapsed. If the
collision occurs during either the preamble or SFD, then these fields will be completed prior to generation
of the jam sequence.
The back off time is based on an XOR of the 10 least significant bits of the data coming from the transmit
FIFO interface and a 10-bit pseudo random number generator. The number of bits used depends on the
number of collisions seen. After the first collision 1 bit is used, then for the second collision 2 bits and so
on up to the maximum of 10 bits. All 10 bits are used above ten collisions. An error will be indicated and
no further attempts will be made if 16 consecutive attempts cause a collision. This operation is compliant
with the description in Clause 4.2.3.2.5 of the IEEE Std 802.3 standard which refers to the truncated
binary exponential back of algorithm.
In 10/100 MBit/s mode, both collisions and late collisions are treated identically and back off and retry will
be performed up to 16 times.
In all modes of operation, if the TX DMA under runs, a bad CRC is automatically appended using the
same mechanism as jam insertion and the TX_ER signal is asserted. For a properly configured system
this should never happen and also it is impossible if configured to use the DMA with packet buffers, as the
complete frame is buffered in TX Packet Buffer Memory.
By setting bit 28 in the Network Configuration register the IPG may be stretched beyond 96 bits
depending on the length of the previously transmitted frame and the value written to the IPG Stretch
register. Bits [7:0] of the IPG Stretch register multiplied with the previous frame length (including
preamble) bits [15:8] (1 added so as not to get a divide by zero) divides the frame length to generate the
IPG. The IPG Stretch register cannot be used to shrink the IPG below 96 bits.