Cypress S6J3200 Series, Manual

Page: 294 / 1355

CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 293
5.1.
A/D Channel Control Registers (ADC12Bn_CHCTRL0 to 63)
The A/D Channel Control Registers configure the logical channel specific settings. ADC12Bn_CHCTRL0
(described here) is dedicated to channel 0, ADC12Bn_CHCTRL63 is dedicated to channel 63. Other
registers (ADC12Bn_CHCTRL1,.....ADC12Bn_CHCTRL62) have similar bit fields.
REGISTER_NAME ADC12Bn_CHCTRLi (i = 0 to 63)
OFFSET i*4
ACCESS_SIZE B H W
MULTIPLE 0:63
NUMERIC_TYPE
-
OTHER
-
A/D Channel Control Register (ADC12Bn_CHCTRL0)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved TRGCL SWTRG
ACCESS_TYPE R0,W0 R0,W R0,W
PROT_TYPE
INITIAL_VALUE 0x00 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME RCEN RCINVSEL Reserved RCSEL[2] RCSEL[1] RCSEL[0] SMTIME[1] SMTIME[0]
ACCESS_TYPE R/W R/W R0,W0 R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME Reserved DP RSMRST[1] RSMRST[0] CHPRI[3] CHPRI[2] CHPRI[1] CHPRI[0]
ACCESS_TYPE R0,W0 R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME TRGTYP[1] TRGTYP[0] ANIN[5] ANIN[4] ANIN[3] ANIN[2] ANIN[1] ANIN[0]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:26] Reserved : Reserved bits
When writing, always write "0".
When reading, "0" is always read.