Cypress S6J3200 Series, Manual

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CHAPTER 22:Media Local Bus Interface (MediaLB)
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 831
4.
Registers
The MediaLB module contains various registers to configure its operation, to monitor its status and, when
configured in IO Mode, to access the receive and transmit data buffers.
The MediaLB module is allocated 1KB of MCU address space for mapping the Configuration and Status
Registers (i.e. CSRs). The address area allocated to MediaLB and the Control and Status Registers in
MediaLB are explained in this section.
The suffix ‘n’ in the register name indicates that the register is an instance ‘n’ of the module.
Registers of MediaLB
The following registers are available for each instance of MediaLB:

MediaLBn Device Control Configuration Register (MLBn_DCCR)

MediaLBn System Status Configuration Register (MLBn_SSCR)

MediaLBn System Data Configuration Register (MLBn_SDCR)

MediaLBn System Mask Configuration Register (MLBn_SMCR)

MediaLBn Version Control Configuration Register (MLBn_VCCR)

MediaLBn Synchronous Base Address Configuration Register (MLBn_SBCR)

MediaLBn Asynchronous Base Address Configuration Register (MLBn_ABCR)

MediaLBn Control Base Address Configuration Register (MLBn_CBCR)

MediaLBn Isochronous Base Address Configuration Register (MLBn_IBCR)

MediaLBn Channel Interrupt Configuration Register (MLBn_CICR)

MediaLBn AHB Master Control Register (MLBn_AHBMCTL)

MediaLBn Channel Entry Configuration Register (MLBn_CECR0 - MLBn_CECR15)

MediaLBn Channel Status Configuration Register (MLBn_CSCR0 - MLBn_CSCR15)

MediaLBn Channel Current Buffer Configuration Register (MLBn_CCBCR0 - MLBn_CCBCR15)

MediaLBn Channel Next Buffer Configuration Register (MLBn_CNBCR0 - MLBn_CNBCR15)

MediaLBn Local Channel Buffer Configuration Register (MLBn_LCBCR0 - MLBn_LCBCR15)

MediaLBn Module Identification Register (MLBn_MID)