Cypress S6J3200 Series, Manual

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CHAPTER 22:Media Local Bus Interface (MediaLB)
854 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.8.
MediaLBn Control Base Address Configuration Register (MLBn_CBCR)
MediaLBn Control Base Address Configuration Register (MLBn_CBCR) defines the base address for
control receive/transmit system memory buffers.
REGISTER_NAME YOURPERIn_CSRi
OFFSET 0 + i*4
ACCESS_SIZE B H W
MULTIPLE 0:15
NUMERIC_TYPE
OTHER
MediaLB Control Base Address Configuration Register (MLBn_CBCR)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME CRBA[15] CRBA[14] CRBA[13] CRBA[12] CRBA[11] CRBA[10] CRBA[9] CRBA[8]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME CRBA[7] CRBA[6] CRBA[5] CRBA[4] CRBA[3] CRBA[2] CRBA[1] CRBA[0]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME CTBA[15] CTBA[14] CTBA[13] CTBA[12] CTBA[11] CTBA[10] CTBA[9] CTBA[8]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME CTBA[7] CTBA[6] CTBA[5] CTBA[4] CTBA[3] CTBA[2] CTBA[1] CTBA[0]
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:16] CRBA[15:0] : Upper Half of Control Receive Base Address for DMA mode
These bits allow the system software to define the base address (CRBA[31:16]) for control receive
system memory buffers.
This base address is shared by all control receive channels and defines the upper 16 bits of the 32-bit
system bus address for these channels.
This bit field is only used in DMA mode. In IO mode these bits are not used.