Cypress S6J3200 Series, Manual

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CHAPTER 3:Product Description
44 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Feature Description
Ethernet AVB
10/100 Mbps
MII-Interface
Supports Audio-Video Bridging (AVB)
ETHERNETn_revision_reg :
0x30070106 (Initial value) for after revision B
ETHERNETn_designcfg_debug6 :
0x0302000E (Initial value)
See 2.1 in details.
MediaLB
MOST25 (512FS)
3 wires
Maximum 15ch is available.
LCD Controller
TEQFP256 : 4com x 32seg
TEQFP216 : 4com x 32seg
TEQFP208 : 4com x 30seg
LCDC pins are initialized with Reset. (Stop LCDC alternating current output).
Duty and Static of segment output is supported. (SEG23/ST0, SEG24/ST1, SEG25/ST2, SEG26/ST3,
SEG27/ST4, SEG28/ST5, SEG29/ST6, SEG30/ST7, SEG31/ST8)
SHE See the platform manual in detail.
Source Clock Timer See the platform manual in detail.
Graphics Subsystem
Variable setting about GDC clock. (Asynchronous with CPU clock)
Two drawing engines for “2D drawing” and “3D drawing”. Parallel processing support.
CPU can direct access to VRAM.
Programmable panel timing controller with RGB888 and RSDS support.
FPD-Link Converter
LFCTRL and FRANGE bit of CTRL1. See chapter FPD-Link Converter about function.
-
These register bit are supported for revision H, M and P
-
These register bit are not supported for revision E, F and J. These bit are reserved bit(Access type is
R0,W0. Initial value is 0).
Power Supply Control
(PSC)
PSC (PSC_1) output is used for external 1.2-V power supply module control and automatically switched
with the following condition.
"High": Request to supply VCC12
- "Power ON Reset" is released
- CPU wakes up from PSS shutdown mode
"Low": Request to stop supplying VCC12
- CPU transfers from RUN mode to PSS shutdown mode.
For timing chart of output signals include PSC in detail, see the "S6J3200 hardware manual" and chapter
"State Transition"