Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 673
4.22.
Specific Address Bottom i Register
(ETHERNETn_spec_add_bottom_i) (i=1 to 4)
The address stored in the Specific Address i registers are deactivated at reset or when their
corresponding Specific Address Bottom i register is written. They are activated when Specific Address
Top i register is written.
REGISTER_NAME ETHERNETn_spec_add_bottom_i
OFFSET (0x088 + ((i-1)*0x8))
ACCESS_SIZE W
MULTIPLE 1:4
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME address[31:24]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME address[23:16]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME address[15:8]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME address[7:0]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00
[bit31:0] address: Specific address i [31:0]
Least significant 32 bits of the destination address, which is bits [31:0]. Bit 0 indicates whether the
address is multicast or unicast and corresponds to the least significant bit of the first byte received.