Cypress S6J3200 Series, Manual

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CHAPTER 27:HyperBus Interface
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1029
[bit15:12] RCSH[3:0] : Read Chip Select Hold After CK falling Edge
In the read access, this bit inserts the CK cycles, between the falling edge of last CK and the rising
edge of chip select.
[bit11:8] WCSH[3:0] : Write Chip Select Hold After CK falling Edge
In the write access, this bit inserts the CK cycles, between the falling edge of last CK and the rising
edge of chip select.
Bits Description
0000 1 CK
0001 2 CK
0010 3 CK
:
: :
:
1111 16 CK
[bit7:4] RFU : Reserved for Future Use
When writing this register, this bit should be set to 0 for future compatibility. When reading this register,
this bit is 0 for future compatibility.
[bit3:0] LTCY[3:0] : Latency Cycle for HyperRAM mode
When DEVTYPE of HYPERBUSI_MCRn is set to HyperRAM mode, this bit should be set to the same
value as the read latency in configuration register of HyperBus memory. This bit is ignored when the
DEVTYPE of HYPERBUSI_MCRn is chosen to HyperFlash mode.
Bits Description
0000 5 CK Latency
0001 6 CK Latency
0010 Reserved
:
: :
:
1110 3CK Latency
1111 4 CK Latency
Bits Description
0000 1 CK
0001 2 CK
0010 3 CK
:
: :
:
1111 16 CK