Cypress S6J3200 Series, Manual

Page: 1347 / 1355

CHAPTER 37:Major Changes
1346 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Summary
E
rror
P
age
Error
C
orre
ct
P
age
Correct ID
Ethernet
Description
634
[bit2] man_done: Management
doneWhen this bit is set it means PHY
management logic is idle (i.e. has
completed).[bit1] mdio_in: MDIO_IN
statusThis bit returns the status of the
mdio_in pin.[bit0] ReservedAlways read
"0". Writing has no effect.
624
[bit2] retry_limit_exceeded: Retry limit
exceededCleared by writing a one to this
bit.[bit1] collision_occurred: Collision
occurredSet by the assertion of collision.
Cleared by writing a one to this bit. When
operating in 10/100 mode, this status
indicates either a collision or a late
collision. In gigabit mode, this status is not
set for a late collision.[bit0] used_bit_read:
Used bit readSet when a transmit buffer
descriptor is read with its used bit set.
Cleared by writing a one to this bit.
#395
Ethernet
Description
644
bit29:enable_tsu_timer_comparisoninterr
upt
bit27:enable_rx_lpi_idication_status_bit_c
hange
634
bit29:enable_tsu_timer_comparison_inter
rupt
bit27:enable_rx_lpi_indication_interrupt
#421
Ethernet
Description
645
[bit27]
enable_receive_lpi_indication_status_bit_
change: Enable Receive LPI Indication
Status Bit change Always read "0".
Writing "1" enables Receive LPI Indication
Status Bit change interrupt.
635
[bit27] enable_rx_lpi_indication_interrupt:
Enable RX LPI indication interrupt
#497
Ethernet
Description
647
bit29:disable_tsu_timer_comparisoninterr
upt
bit27:disable_rx_lpi_idication_status_bit_
change
634
bit29:disable_tsu_timer_comparison_inter
rupt
bit27:disable_rx_lpi_indication_interrupt
#496
Ethernet
Description
648
[bit27]
disable_receive_lpi_indication_status_bit
_change:Disable Receive LPI Indication
Status Bit change
Writing "1" disables Receive LPI
Indication Status Bit change interrupt.
638
[bit27] disable_rx_lpi_indication_interrupt:
Disable RX LPI indication interrupt
#498
Ethernet
Description
650-
655
-
640-
645
(Revised the bit name and description in
4.12 Interrupt Mask Register)
#423
Ethernet
description
804 - 795 (Added the 5. Functional Limitations) #511
DAC clock
description
869
CLKPI ≥ CLKDA / 17
861
CLKPI ≥ CLKDA / 17
FIFO operates with CLKPI, and the
portion of analog circuit does with CLKDA.
Then, CLKDA should be fast enough for
data to be transferred from FIFO to
analog circuit.
#218