Cypress S6J3200 Series, Manual

Page: 680 / 1355

CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 679
4.27.
Transmit PFC Pause Register (ETHERNETn_tx_pfc_pause)
Description of Transmit PFC Pause register is shown.
REGISTER_NAME ETHERNETn_tx_pfc_pause
OFFSET 0x0C4
ACCESS_SIZE W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME vector[7:0]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME vector_enable[7:0]
ACCESS_TYPE R/W
PROT_TYPE Wp
INITIAL_VALUE 0x00
[bit31:16] Reserved
Always read "0". Writing has no effect.
[bit15:8] vector: Priority vector pause size
If bit 17 of the Network Control register is written with a "1" then for each entry equal to "0" in the
Transmit PFC Pause register [15:8], the PFC pause frame's pause quantum field associated with that
entry will be taken from the Transmit Pause Quantum register. For each entry equal to "1" in the
Transmit PFC Pause register [15:8], the pause quantum associated with that entry will be "0".