CHAPTER 21:Ethernet MAC
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S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
For IP, TCP, and UDP checksum offload to be useful, the operating system containing the protocol stack
must be aware that this offload is available so that it can make use of the fact that the hardware can either
generate or verify the checksum.
3.4.1.
Receiver Checksum Offload
When receive checksum offloading is enabled in the Ethernet MAC, the IPv4 header checksum is
checked as per RFC 791, where the packet meets the following criteria:
−
If present, the VLAN header must be four octets long and the CFI bit must not be “1”. (Also for
receive one stacked VLAN is supported.)
−
Encapsulation must be RFC 894 Ethernet Type Encoding or RFC 1042 SNAP Encoding or PPPoE
Encoding.
−
IPv4 packet.
−
IP header is of valid length.
−
IP options are supported.
The Ethernet MAC also checks the TCP checksum as per RFC 793, or UDP checksum as per RFC 768, if
the following criteria are met:
−
IPv4 or IPv6 packet.
−
IP options and all IPv6 extension headers (i.e. hop-by-hop, routing and destination) are supported
(except for fragmentation headers).
−
Good IP header checksum (if IPv4).
−
IP fragmentation is not supported. (If a packet is fragmented, then the checksum will not be
checked)
−
TCP or UDP packet.
When an IP, TCP, or UDP frame is received, the receive buffer descriptor gives an indication if the
Ethernet MAC was able to verify the checksums. There is also an indication if the frame had SNAP
encapsulation. These indication bits will replace the Type ID match indication bits when the receive
checksum offload is enabled. For details of these indication bits refer to table
If any of the checksums are verified incorrect by the Ethernet MAC, the packet is discarded and the
appropriate statistics counter incremented.
3.4.2.
Transmitter Checksum Offload
The transmitter checksum offload is only available if the Ethernet MAC is configured to use the DMA in
packet buffer mode and full store and forward mode is enabled. This is because the complete frame to be
transmitted must be read into the TX Packet Buffer Memory before the checksum can be calculated and
written back into the headers at the beginning of the frame.
Transmitter checksum offload is enabled by setting bit 11 in the DMA Configuration register. When
enabled, it will monitor the frame as it is written into the TX Packet Buffer Memory to automatically detect
the protocol of the frame. Protocol support is identical to the receiver checksum offload.
For transmit checksum generation and substitution to occur, the protocol of the frame must be recognized
and the frame must be provided without the FCS field, by making sure that bit 16 of the transmit
descriptor Word 1 is clear (VLAN tagged frames will be recognized but stacked VLAN tagged frames will
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