Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
604 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
The Ethernet MAC contains a timestamp unit (TSU) which consists of a timer and registers to capture the
time at which PTP event frames cross the message timestamp point. The registers are accessible
through the Ethernet MAC’s APB slave interface. An interrupt is issued when a capture register is
updated.
3.6.1.
Support for Time Stamping and Timestamp Accuracy
The MAC has the responsibility of sampling the TSU timer value when the TX or RX SOF event of the
frame passes the MII boundary. This event is an existing signal synchronous to MAC TX/RX clock
domains. The MAC uses the sampled timestamp to insert the timestamp into transmitted PTP Sync
frames (if one step sync feature is enabled), or to pass to the Ethernet MAC’s register block to capture the
timestamp (TS) in registers, or to pass to the Ethernet MAC DMA to insert into TX or RX buffer descriptors.
For each of these, the SOF event, which is captured in the TX and RX clock domains respectively, is
synchronized to the TSU clock domain and the resulting signal is used to sample the TSU count value.
This value will be kept stable for an entire frame, or specifically at least 64 TX/RX clock cycles, since the
minimum frame size in Ethernet is 64 bytes and worst case is a transfer rate of 1 byte per cycle. It is used
as the source for all the components within the Ethernet MAC that require the timestamp value. Since the
SOF event had to pass a clock boundary, there is a degree of inaccuracy in the captured timestamp. The
level of inaccuracy depends on the frequency of the TSU clock (tsu_clk). There will be no more than 1
clock cycle of inaccuracy.
In the best case, the SOF event (which is in the TX/RX clock domain) just meets the setup time of the
TSU clock domain at the input to the first synchronization FlipFlop. The captured TS is N+2, but it really
should be N+1. In the worst case, the captured TS is also N+2, but it really should be N.
3.6.2.
Single Step Time Stamping
Support of one step clock for TX Sync frames can be enabled by setting bit 24 in the Network Control
register. In this mode the timestamp field, within the IEEE Std 1588 version 2 Sync frame, is replaced by
the TSU timestamp value at the time the Sync frame SOF passes the MII Interface To use single step
time stamping, the sampled timestamp must be stable before the point at which Ethernet MAC requires to
insert the timestamp. This can be guaranteed by enforcing a rule that TSU clock (tsu_clk) is greater than
1/8
th
the frequency of TX clock (TX_CLK) or RX clock (RX_CLK).
3.6.3.
Timestamp Capture in Registers
There are four 80-bit timestamp status registers that capture the time at which PTP event frames are
transmitted and received.
−
{ETHERNETn_tsu_ptp_rx_msb_sec, ETHERNETn_tsu_ptp_rx_sec, ETHERNETn_tsu_ptp_rx_nsec}
−
{ETHERNETn_tsu_ptp_tx_msb_sec, ETHERNETn_tsu_ptp_tx_sec, ETHERNETn_tsu_ptp_tx_nsec}
−
{ETHERNETn_tsu_peer_rx_msb_sec, ETHERNETn_tsu_peer_rx_sec, ETHERNETn_tsu_peer_rx_nsec}
−
{ETHERNETn_tsu_peer_tx_msb_sec, ETHERNETn_tsu_peer_tx_sec, ETHERNETn_tsu_peer_tx_nsec}
An interrupt is issued when these registers are updated.
3.6.4.
Timestamp Capture in DMA Descriptors
The TX and/or RX timestamp can optionally be captured in an extended buffer descriptor when
configured using bits [29:28] in the DMA Configuration register. The timestamp can be captured for a
number of frame types (PTP event or PTP general, or all frames, or none as defined in TX BD Control/RX