Cypress S6J3200 Series, Manual

Page: 1354 / 1355

Revision History
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1353
Revision ECN No. Description of Change
CHAPTER 3: Product Description 2. Product Description
[Improve] Added the information of main oscillation stabilization wait time.
CHAPTER 3: Product Description 2. Product Description
[Improve] Added the register information of "Interrupt Enable Register" (HYPERBUSIn_IEN) for clarifying "not
support".
CHAPTER 3: Product Description 2. Product Description
[Improve] Corrected the number of I2C support ports for MFS.
CHAPTER 3: Product Description 2. Product Description
[Improve] Corrected the stabilization time for embedded CR oscillation.
CHAPTER 3: Product Description 2. Product Description
[Improve] Deleted the unnecessary description for PPU of I2S
CHAPTER 3: Product Description 3.3. Register Initial Value
[Improve] Removed wrong description in LVDH1S.
CHAPTER 10: Port Description 1. Port Description List
[Improve] Added the supplementary information for I2C pin name of SCL, SDA.
CHAPTER 30: FPD-Link Converter 4.3. Control1 Registers (CTRL1)
[Enhance] Updated description for the LFTCTRL[29:28] of the CTRL1 Register
CHAPTER 34: Sound System Configuration 3.3.1. Disabling the Output Module
[Limitation] Added notes in case changing the output module from "enabled" to "disabled"
*E
5978350
CHAPTER 3: Product Description 3.3. Register Initial Value
[Improve] Added the initial value and access type information for PLL and LVD register.
CHAPTER 21: Ethernet MAC 3.1.8. Priority Queuing in the Ethernet MAC DMA
[Improve] Added explanation that lower priority frames can be transmitted before higher priority frames if higher
priority frames are long.
CHAPTER 21: Ethernet MAC 4. Registers
[Improve] Corrected name of bits [14], [25] in 4.9. Interrupt Status Register
[Improve] Corrected name of bits [14], [25], [27] in 4.10. Interrupt Enable Register
[Improve] Corrected name of bits [14], [27] in 4.11. Interrupt Disable Register
[Improve] Corrected name of bits [16:31] in 4.40. Identification and Revision Register
[Improve] Corrected access type of bits [16:31] in 4.46. Pause Frames Transmitted Register
[Improve] Corrected access type of bits [16:31] in 4.66. Pause Frames Received Register
*F 6196400
CHAPTER 2: Function List 2.1 Basic Option Figure 2-1
[Enhance] Added revision P to Figure 2-1
[Enhance] Added remark 1), 2) of revision version to Figure 2-1
CHAPTER 2: Function List 2.1 Basic Option Table 2-1 Note
[Improve] Removed
description of sub clock limitation
CHAPTER 2: Function List 2.1 Basic Option Figure 2-2
[Improve] Removed the information of Option Digit U for S6J320A
CHAPTER 2: Function List 2.1 Basic Option Table 2-2
[Improve] Removed the information of Function Digit A, C, D for S6J320E Series
CHAPTER 2: Function List 2.1 Basic Option Figure 2-3
[Improve] Removed the information of Option Digit U for S6J320E
CHAPTER 2: Function List 2.2 ID
[Enhance] Added the ID information of Revision Digit P for S6J320C Series