Revision History
1350
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Revision
ECN No.
Description of Change
CHAPTER 12: State Transition, 2.Diagram of State Transition, 2nd table in Figure 2-2
[Improve] Added PD4_0/1 ON or OFF in PSS mode.
CHAPTER 12. State Transition 3. Fetching the Operation Mode
[Enhance] Added max VCC12 stabilization time to Figure 3-1
CHAPTER 12. State Transition 3. Fetching the Operation Mode
[Enhance] Added to Figure 3-1 a table explaining which reset is asserted during the power-up of each supply
CHAPTER 12: State Transition 4. Changes to PSS and RUN
[Enhance] Added signals PSC1 and VCC12 to Figure 4-1.
CHAPTER 13: Low-voltage Detection 4. Registers
[Enhance] Added notes about Guaranteed MCU operation range
CHAPTER 13: Low-voltage Detection 4. Registers
[Enhance] Added notes for LVDH1S bit.
CHAPTER 13: Low-voltage Detection 4. Registers
[Improve] [bit26:25] LVDL1V=01 : 0.87V => [bit26:25] LVDL1V=01 : Not supported
CHAPTER 13:Low-voltage Detection 4. Registers
[Improve] Corrected revision information for additional revision. (1 for B -> 1 for any revision other than A)
CHAPTER 13:Low-voltage Detection 4.Registers
[enhance] Added notes to avoid switching noise problem.
CHAPTER 15: 12-/10-/8-bit Analog to Digital Converter 3.1. A/D Conversion Flow
[Improve] (4) Conversion => (4) Comparison
CHAPTER 15: 12-/10-/8-bit Analog to Digital Converter 5.4. Pulse Counter Control Registers
(ADC12Bn_PCCTRL0 to 63)
[Improve] Corrected bit explanation of "PCTNRL[4:0]" ( ADC12Bn_PCIRQC0.PCIRQC0 bit ->
ADC12Bn_PCIRQC0 to 1.PCIRQC bit )
[Improve] Corrected bit explanation of "PCTPRL[7:0]" ( ADC12Bn_PCIRQC0.PCIRQC0 ->
ADC12Bn_PCIRQC0 to 1.PCIRQC )
CHAPTER 15: 12-/10-/8-bit Analog to Digital Converter 5.4. Pulse Counter Control Registers
(ADC12Bn_PCCTRL0 to 63)
[Improve] Corrected bit explanation of "PCTPCT[7:0]" (ADC12Bn_PCIRQC0.PCIRQ bit -> ADC12Bn_PCIRQC0
to 1.PCIRQC bit, ... reload negative counter ... -> ... reload positive counter ... )
CHAPTER 15: 12-/10-/8-bit Analog to Digital Converter Figure 3 11 Restarting of the Group Processing with a
Subgroup
[Improve] Corrected typo in 4th description for Figure 3-11 Restarting of the Group Processing (Restart to ch0
=> Restart to ch1 : because ch1 RSMRST = 01b)
CHAPTER 19: Sound Waveform Generator 3.1.6. Fade Out Time (RELEASE)
[Improve] Corrected the condition of Attack and Release configuration
CHAPTER 19: Sound Waveform Generator 3.2. Interrupt
[Improve] Deleted the description of "SWFG AHB Master Interface access error"
CHAPTER 20: Sound Mixer 4.4. Mixer Input Control Register (MXICTRL)
[Improve] Corrected the bit name of [bit6:4] (PMIS1REQ -> PMIS1FREQ)
CHAPTER 20:Sound Mixer 4.7. Mixer Channel Volume2 Register (MXCHVOL2)
[Improve] Corrected the register name (PMIS2VOL -> PMIS0VOL)
CHAPTER 20: Sound Mixer 4.24. Mixer Channel Buffer Count Register (MXCHBUFFCNT)
[Improve] Corrected the bit name of [bit19:16] and [bit11:8] in register table (PMI2CNT, PMI0CNT -> PMIS2CNT,
PMIS0CNT)
Summary of Contents for S6J3200 Series
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