CHAPTER 20:Sound Mixer
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
501
3.
Operation of the Sound Mixer
3.1.
Basic Mixing Operation Procedure
3.1.1.
Mixing Start
The mixing procedure started by sound mixing is shown below.
1. Disable input of the sound source. See MXCH under 4.1.
2. Set the output destination address and number of transfers of the mix sound source. See MXOCTRL
under 4.2.
3. Configure sound source input channel PMIS0 through 4 sampling rate settings. See MXICTRL under
4.4.
4. Configure sound source input channel PMIS0 through 4 sound source process mode settings. See
MXCHMONO under 4.5.
5. Initialize the sound source input channel PMIS0 through 4 input buffers. Also, initialize the mixed sound
source output buffer. See MXBUFFCLR under 4.17.
6. Enable sound source input. See MXCH under 4.1.
7. Configure DMA transfer request and data transfer request interrupt threshold value settings for sound
input channels PMIS0 through 4. See MXDRQCTRL under 4.3.
8. Configure interrupt enable/disable settings. See MXINTREN under 4.19.
9. Start sound source input.
Notes:
−
The settings in steps 3, 4 and 7 are not required for sound source input channels WFG0 through
4. Also, other settings equivalent to these settings are not configured.
−
Configure the input channels with the above settings in sequence from 1 through 9 in order to
add new sound source input to an ongoing sound mixer operation and perform consecutive
mixing. However, the output destination setting in step 2 is not required.
−
The number of transfers of mixed sound sources from the sound mixer must match the number of
output destination transfer requests. When the number of transfers on the sound mixer side is
greater, the output destination will generate a DMA transfer error. When the number of transfer
requests on the output destination side is greater, the output destination will not issue a DMA
transfer request.
−
If a sound source is not input on the actual device a sound source input is enabled, mixing is
stopped for all channels (not only on the applicable channel).
−
In the step 5, completion of the initialization is required before executing the next step.
Completion can be confirmed by reading the applicable bit of the MXBUFFCLR register, because
the bit is automatically cleared to 0 following initialization.
Summary of Contents for S6J3200 Series
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