Cypress S6J3200 Series, Manual

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CHAPTER 22:Media Local Bus Interface (MediaLB)
874 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
beginning address of the Next Buffer in system memory. Once system software detects
MLBn_CSCRn.RDY has been cleared by hardware (for ping-pong buffering), the beginning address of
the Next Buffer may be loaded into BSA[15:2]. System software should then set MLBn_CSCRn.RDY.
Once processing of the Current Buffer for the logical channel is complete, the BSA[15:2] field is loaded
into the MLBn_CCBCRn.BCA[15:2] field and processing of the next buffer can begin. This Next Buffer
address pointer must always be quadlet aligned (e.g., BSA[1:0] must be written as "00").
The upper half of the beginning address of the Next Buffer in system memory is defined by
MLBn_SBCR.SRBA, MLBn_ABCR.ARBA, MLBn_CBCR.CRBA, or MLBn_IBCR.IRBA when
MLBn_CECRn.TR is clear; MLBn_SBCR.STBA, MLBn_ABCR.ATBA, MLBn_CBCR.CTBA, or
MLBn_IBCR.ITBA when MLBn_CECRn.TR is set, dependant on the value of MLBn_CECRn.CT[1:0].
Note:
−
For BSA[1:0] bits in DMA mode, read value is "X". Write always "0" to these bits.
In IO mode, this bit field defines the Transmit Data Buffer bits - TDB[31:16].
This field contains the upper half of the next quadlet of transmit data when the logical channel is
configured as transmit channel.
[bit15:0] BEA[15:0] : Buffer End Address bits
This bit field has different interpretations for DMA mode and IO mode.
In DMA mode, the BEA field defines a 16-bit address pointer, which identifies the lower half of the ending
address of the Next Buffer in system memory. Once system software detects MLBn_CSCRn.RDY has
been cleared by hardware (for ping-pong buffering), the ending address of the Next Buffer may be loaded
into BEA[15:2]. System software should then set MLBn_CSCRn.RDY. Once processing of the Current
Buffer for the logical channel is complete, the BEA[15:2] field is loaded into the
MLBn_CCBCRn.BFA[15:2] field and processing of the next buffer can begin. The BEA[15:2] bits are
loaded into MLBn_CCBCRn.BFA[15:2] when the Current Buffer is finished being processed. This Next
Buffer address pointer, except when associated with isochronous channels, should always be quadlet
aligned (i.e., set BEA[1:0] to "00" for Synchronous, Asynchronous and Control channels).
The upper half of the ending address of the Next Buffer in system memory is defined by
MLBn_SBCR.SRBA, MLBn_ABCR.ARBA, MLBn_CBCR.CRBA, and MLBn_IBCR.IRBA when
MLBn_CECRn.TR is clear; MLBn_SBCR.STBA, MLBn_ABCR.ATBA, MLBn_CBCR.CTBA, or
MLBn_IBCR.ITBA when MLBn_CECRn.TR is set, dependant on the value of MLBn_CECRn.CT[1:0].
In IO mode, this bit field defines the Transmit Data Buffer bits - TDB[15:0].
This field contains the lower half of the next quadlet of transmit data when the logical channel is
configured as transmit channel.