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Cypress S6J3200 Series, Manual

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CHAPTER 23:Stereo Audio DAC 

 
 

S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 

895 

4.5. 

DAC FLUSH Register(DAFLUSH) 

This DAFLUSH Register is the initialization of DATA FIFO. 

REGISTER_NAME 

DAC FLUSH Register(DAFLUSH) 

OFFSET 

0x010 

ACCESS_SIZE 

B H W 

MULTIPLE 

0 

NUMERIC_TYPE 

 

OTHER 

 

 

BIT_OFFSET 

31 

30 

29 

28 

27 

26 

25 

24 

BIT_NAME 

Reserved 

Reserved 

Reserved 

Reserved 

Reserved 

Reserved 

Reserved 

Reserved 

ACCESS_TYPE 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

PROT_TYPE 

Wp 

INITIAL_VALUE 

0 

0 

0 

0 

0 

0 

0 

0 

 

BIT_OFFSET 

23 

22 

21 

20 

19 

18 

17 

16 

BIT_NAME 

Reserved 

Reserved 

Reserved 

Reserved 

Reserved 

Reserved 

Reserved 

Reserved 

ACCESS_TYPE 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

PROT_TYPE 

Wp 

INITIAL_VALUE 

0 

0 

0 

0 

0 

0 

0 

0 

 

BIT_OFFSET 

15 

14 

13 

12 

11 

10 

9 

8 

BIT_NAME 

Reserved 

Reserved 

Reserved 

Reserved 

Reserved 

Reserved 

Reserved 

Reserved 

ACCESS_TYPE 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

PROT_TYPE 

Wp 

INITIAL_VALUE 

0 

0 

0 

0 

0 

0 

0 

0 

 

BIT_OFFSET 

7 

6 

5 

4 

3 

2 

1 

0 

BIT_NAME 

Reserved 

Reserved 

Reserved 

Reserved 

Reserved 

Reserved 

Reserved 

FLUSH 

ACCESS_TYPE 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

R0,W0 

R0,W1 

PROT_TYPE 

Wp 

INITIAL_VALUE 

0 

0 

0 

0 

0 

0 

0 

0 

 

[bit31:1] Reserved 

This bit is reserved.   

Always write "0" to this bit. The read value is "0". 

 

[bit0] FLUSH: FIFO FLUSH 

Explanation of FIFO FLUSH 

Bit 

Description 

0 

No change 

1 

Enable FIFO FLUSH Mode 

Summary of Contents for S6J3200 Series

Page 1: ...rs as part of the Infineon product portfolio Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes t...

Page 2: ...32 bit Microcontroller Traveo Family S6J3200 Series Hardware Manual Document Number 002 04852 Rev G Cypress Semiconductor 198 Champion Court San Jose CA 95134 1709 www cypress com...

Page 3: ...er liability arising from any Security Breach In addition the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from pub...

Page 4: ...d Intended Readers This manual explains the functions and operations of this family and describes how it is used The manual is intended for engineers engaged in the actual development of products usin...

Page 5: ...ID 36 2 3 Restriction 36 CHAPTER 3 Product Description 38 1 Overview 39 2 Product Description 39 2 1 Ethernet 45 2 2 Reset Signal 45 3 Note 47 3 1 Status Flag Clear 47 3 2 Error Response 47 3 3 Regis...

Page 6: ...put Drive Capacity Setting 209 3 6 Port Status 213 3 7 Function Port Group 214 3 8 Key Code Register 217 4 Registers 218 5 Configuration Procedure 218 5 1 Resource I O Port Both Direction 219 5 2 Reso...

Page 7: ...ntrol of A D Conversion 283 4 2 Setting of Global A D Conversion 284 4 3 Setting of Logical Channel 285 4 4 Setting of Range Comparator 286 4 5 Setting of Pulse Detection 287 4 6 A D Conversion 288 4...

Page 8: ...er Global Control Register ADC12Bn_CTRL 358 5 29 A D Converter Global Status Register ADC12Bn_STAT 361 5 30 Range Comparator Upper Threshold Registers ADC12Bn_RCOH0 to 7 363 5 31 Range Comparator Lowe...

Page 9: ...nd Decrease Data Register SGIDR 454 4 8 PWM Cycle Data Register SGPCR 455 4 9 DMA Transfer Intermediate Register SGDMAR 456 4 10 Interrupt Clear Register SGCCR 458 CHAPTER 19 Sound Waveform Generator...

Page 10: ...r MXCHMONO 517 4 6 Mixer Channel Volume1 Register MXCHVOL1 519 4 7 Mixer Channel Volume2 Register MXCHVOL2 520 4 8 Mixer Channel Volume3 Register MXCHVOL3 521 4 9 Mixer Channel Mute Register MXCHMUTE...

Page 11: ...ETHERNETn_transmit_status 634 4 6 RX Buffer Queue Base Address Register ETHERNETn_receive_q_ptr 636 4 7 TX Buffer Queue Base Address Register ETHERNETn_transmit_q_ptr 638 4 8 Receive Status Register...

Page 12: ...47 32 Register ETHERNETn_tsu_peer_rx_msb_sec 693 4 40 Identification and Revision Register ETHERNETn_revision_reg 694 4 41 Octets Transmitted Bottom Register ETHERNETn_octets_txed_bottom 695 4 42 Octe...

Page 13: ...rsize Frames Received Register ETHERNETn_excessive_rx_length 730 4 76 Jabbers Received Register ETHERNETn_rx_jabbers 731 4 77 Frame Check Sequence Errors Register ETHERNETn_fcs_errors 732 4 78 Length...

Page 14: ...RNETn_designcfg_debug8 774 4 114 Design Configuration 9 Register ETHERNETn_designcfg_debug9 776 4 115 Design Configuration 10 Register ETHERNETn_designcfg_debug10 778 4 116 Interrupt Status Queue i Re...

Page 15: ...Register MLBn_DCCR 837 4 2 MediaLBn System Status Configuration Register MLBn_SSCR 841 4 3 MediaLBn System Data Configuration Register MLBn_SDCR 844 4 4 MediaLBn System Mask Configuration Register ML...

Page 16: ...errupt State Register INTRSTAT 899 4 8 Interrupt Clear Register INTCTR 901 4 9 DAC Polarity Configuration Register DPCR 903 4 10 Data 0 15 Register DADR 905 CHAPTER 24 Inter IC Sound I2S 906 1 Overvie...

Page 17: ...3 3 1 Description of the PCM to PWM Conversion Process 983 3 2 PWM Cycle Time Configuration 988 3 3 PCM Data Sample Input 988 3 4 Interrupts 989 3 5 Dead Timer Operation 989 4 Registers 990 4 1 PCMPWM...

Page 18: ...Switching Register LCDCMR 1059 6 5 LCDC Static Control Register LCRS 1060 6 6 Static LCD Display Data Register LDR 1062 6 7 Key Code Register LCD_KEYCDR 1064 6 8 Segment Output Register SEGER 1067 6...

Page 19: ...cessing a Register 1115 5 2 Indicator PWM Operation Precautions 1115 CHAPTER 30 FPD Link Converter 1116 1 Overview 1117 2 Configuration and Block Diagram 1117 3 Operation 1119 3 1 Register IF 1119 3 2...

Page 20: ...PUHn_CTRL1 to 8 1176 4 6 MPU AHB Start Address Registers MPUHn_SADDR1 to 8 1177 4 7 MPU AHB End Address Registers MPUHn_EADDR1 to 8 1178 4 8 MPU AHB Unlock Register MPUHn_UNLOCK 1179 4 9 MPU AHB Modul...

Page 21: ...05 4 3 Interface between SMIX and I2S 1306 4 4 Interface between SWFG and SMIX 1307 4 5 Interface between DMAC and SMIX 1307 4 6 Interface between CPU and SMIX 1308 5 Note 1308 CHAPTER 35 Base Timer P...

Page 22: ...ies Hardware Manual Document Number 002 04852 Rev G 21 CHAPTER 1 Overview This chapter explains the product overview 1 Overview 2 Document Definition 3 Register Attribute 4 Abbreviation CODE OVERVIEW...

Page 23: ...ation of CPU core platform are described Software engineer 002 04854 Revision Application note The reference software sample application the reference board design and so on are explained Software and...

Page 24: ...otes The register attribute of a status register which has its clear register and set register is conveniently described to be R W though the written value cannot be read directly In this case R W has...

Page 25: ..._OFFSET The bit offset Ex 31 30 29 0 BIT_NAME The bit name ACCESS_TYPE The allowed access defined 3 1 PROT_TYPE The allowed access defined 3 2 INITIAL_VALUE The initial value 4 Abbreviation Abbreviati...

Page 26: ...n Unit IRC InteRrupt Controller IRQ InteRrupt Request ISR Interrupt Service Routine JTAG Joint Test Action Group LLPP Low Latency Peripheral Port LVD Low Voltage Detector MCU MicroController Unit MFS...

Page 27: ...ion SMC Stepper Motor Controller SMIX Sound Mixer SPI Serial Peripheral Interface SRAM Static RAM SSCG Spread Spectrum Clock Generation SWFG Sound Waveform Generator SW WDT Software Watchdog Timer SYS...

Page 28: ...S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 27 CHAPTER 2 Function List This chapter explains the functions 1 Function List 2 Optional Function CODE FUNCTIONLIST S6J3200 E1...

Page 29: ...CR oscillation Slow clock 100kHz Fast clock 4MHz Center frequency See AC specification on the datasheet PLL PLL0 1 2 3 SSCG PLL SSCG0 1 2 3 Clock supervisor Available DMA 16 ch Boot ROM 16 Kbytes JTAG...

Page 30: ...unit 24channels of capture Output Compare Unit 12unit 24 channels of compare match Stepping motor controller SMC For 6 gauges 12bit A D converter Option 1 unit x 50 input ports Max See 2 3 CRC 4 unit...

Page 31: ...deo capture unit Option See 2 1 Video capture format ITU656 YCbCr4 4 4 YCbCr4 2 2 RGB888 RGB666 2D Graphic engine 1 unit 2 5D support Available Vector drawing on 2D engine Available Warping Available...

Page 32: ...Cypress sales representative to receive the product errata notification PEN182201 S 6 J 3 2 0 0 H A A x x x x x x x x Ordering options 7 digit Revision Revision version Digit F Support MCAN 3 2 ISO Ce...

Page 33: ...0 12 16 17 MFS ch 4 10 12 16 17 MFS ch 4 10 12 16 17 MFS ch 4 10 12 16 17 MFS ch 4 10 12 16 17 Notes This table only shows the relations between the optional function and the part numbers That is all...

Page 34: ...stem N A Chip Select Output of MFS N A I2 C MFS ch 16 17 Notes This table only shows the relations between the optional function and the part numbers That is all products are not necessarily available...

Page 35: ...roduct which doesn t support FPD LINK is used for RSDS and DRGB HyperBus Interface ch 0 for MCU and ch 1 for graphic subsystem cannot be used simultaneously 2 1 3 S6J320E Figure 2 3 Option and Part Nu...

Page 36: ...shows the relations between the optional function and the part numbers That is all products are not necessarily available for orders See the order number on the datasheet and confirm actual availabil...

Page 37: ...10200 N A E and F 0x10100101 0x1000C5CF 0x00110200 0x23443420 H 0x10100102 0x1000C5CF 0x00110200 0x23443470 J 0x10100103 0x1000C5CF 0x00110200 0x23443480 M 0x10100104 0x1000C5CF 0x00110200 0x23443490...

Page 38: ...7 P2_28 P2_29 P2_30 P2_31 P3_00 P3_01 P3_02 P3_03 P3_04 P3_05 P3_06 P3_07 P3_08 P3_09 P3_10 P3_11 P3_12 P3_13 P3_14 P3_15 P3_16 P3_17 P3_18 P3_19 P3_20 P3_21 P3_22 P3_23 P3_24 P3_25 P3_26 P3_27 P3_28...

Page 39: ...8 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G CHAPTER 3 Product Description This chapter explains the function feature 1 Overview 2 Product Description 3 Note CODE PRODUCT S6J3200 E...

Page 40: ...n JTAG interface 4k Word Embedded Trace Buffer 4 bit trace support for TEQFP package Full trace dedicated 16 bit port with special bond out package is planned System Control See the platform manual in...

Page 41: ...e PLL SSCG PLL See the platform manual in detail Use case assumption is following PLL Sound system clock Sound frequency master clock Peripherals Display clock Trace clock SSCG CPU core GDC core Hyper...

Page 42: ...t supported Security Chip erase function is available for flash memory The function of MK_CEER is not supported MK_CEER not selectable For details see the platform manual and chapter Security Internal...

Page 43: ...ade in and Fade out control for reverberation Sound Mixer The input channels of 0 4 are reserved for waveform generator Mixing different sampling frequency sounds Mixing Internal sounds and External I...

Page 44: ...r Insertion Control Register FDFECR is not writeable See the platform manual in detail Real Time Clock RTC with Auto calibration See the platform manual in detail DDR High Speed SPI ch 0 HSSPI as a MC...

Page 45: ...s Subsystem Variable setting about GDC clock Asynchronous with CPU clock Two drawing engines for 2D drawing and 3D drawing Parallel processing support CPU can direct access to VRAM Programmable panel...

Page 46: ...GMII SGMII TBI 10 100 1000 Operation 1000 M SGMII Operation Jumbo Frames Physical Control Sub Layer 2 2 Reset Signal The following table shows the reset signal of each function See CHAPTER 4 Reset of...

Page 47: ...Converter CHAPTER 30 RSTX_PD2 Memory Protection Unit for AXI CHAPTER 31 RSTX_PD2 Memory Protection Unit for AHB CHAPTER 32 RSTX_PD2 Graphics Subsystem CHAPTER 33 RSTX_PD2 or GDCCR GRST 2 Except Captur...

Page 48: ...Error Response Error response is generated when access occurs to the following register and bit offset Function Register Bit Offset Access Error Type 12 10 8 BIT ANALOG TO DIGITAL CONVERTER ADC12Bn_C...

Page 49: ...ion Start Address End Address Function Remark 5028_1000 5028_1FFF Hyper Bus ch 2 Control B800_0000 B800_07FF EHTERNET B800_0800 B800_0BFF MPU_AXI This function is supported with ETHERNET B800_8000 B80...

Page 50: ...only if LVDL2V is changed from initial value SYSC0_PSSLVDCFGR LVDL2V R W 00 Greater than 0x0 should be written SYSC0_PSSLVDCFGR LVDL2E R W 0 or 1 See the note below SYSC0_PSSLVDCFGR LVDH1S R W 0 1 sho...

Page 51: ...LL0CGCNTR PLLCGSTP R W 00 SYSC_PLL0CGCNTR PLLCGSSN R W 000000 SYSC_PLL0CGCNTR PLLCGEN R W 1 SYSC_PLL1CGCNTR PLLCGLP R W 11111111 SYSC_PLL1CGCNTR PLLCGSTP R W 00 SYSC_PLL1CGCNTR PLLCGSSN R W 000000 SYS...

Page 52: ...he initial value 3 4 Restriction Function Related Register and Configuration Restriction Remark DDRHSSPI DDRHSSPI Peripheral Communication Configuration Registers DDRHSSPIn_PCC0 3 SS2CD 1 0 00 cannot...

Page 53: ...52 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G CHAPTER 4 Block Diagram This chapter explains the block diagram 1 Block Diagram 2 Note CODE BLOCK_DIAGRAM S6J3200 E1...

Page 54: ...APPLPGR P_SLAVE0 APPS 5 SG 4x Common PERI 1 RLT 4x BT 12x FRT 4x ICU 4x OCU 4x QPRC 2x MFS 5x AHB 32 APB 32 APPLPGRP _SLAVE1 APPS 7 ADC12B SMC 6x SMC_trg LCDC Common PERI 2 RLT 4x BT 0x Port Config CR...

Page 55: ...4 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G CHAPTER 5 Clock Configuration This chapter explains the clock configuration 1 Overview 2 Operation 3 Remark CODE CLOCK_SYSTEM S6J3200 E...

Page 56: ...ore Graphic CLK_CD3A0 SSCG2 See Traveo Platform hardware manual Hyper FLASH CLK_CD1 SSCG3 See Traveo Platform hardware manual CAN CLK_CAN PLL0 See Traveo Platform hardware manual Display clock FPD Lin...

Page 57: ...r Main clock or Sub clock See Traveo Platform hardware manual External interrupt capture unit CLK_EICU Main clock See Traveo Platform hardware manual Real time clock CLK_RTC Main clock See Traveo Plat...

Page 58: ...L3 CLK_CD5 Sound Waveform Generator No Define Waveform Generator and Sound Mixer bus interface clock PLL3 CLK_CD5A0 Sound Waveform Generator No Define Waveform Generator and Sound Mixer operation cloc...

Page 59: ...LCD Controller Sub clock Notes The configuration of the maximum clock frequency above should satisfy the values specified in Datasheet The frequency of CLK_CD5 and CLK_CD5A0 should satisfy the followi...

Page 60: ...2 04852 Rev G 59 2 1 Spread Spectrum Clock Generator SSCG Target frequency of SSCG should be referred in Datasheet Down Spread Mode Figure 2 1 Down Spread Mode Period Time Target ModulationRatio 1 Mod...

Page 61: ...bination of a peripheral function and its source clock you need to see the group name from the table of base address map on this manual at first The group name and its clock source are described in PL...

Page 62: ...S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 61 CHAPTER 6 Operation Mode This chapter explains operation mode 1 Overview 2 Configuration 3 Registers CODE MODE S6J3200 E1...

Page 63: ...mmunication Serial programming mode with asynchronous communication JTAG boundary scan mode 2 Configuration Operation Mode PORT MODE P225 SOT0 P227 SIN0 User Mode 1 Serial Programming Mode Sync 0 1 0...

Page 64: ...e Manual Document Number 002 04852 Rev G 63 CHAPTER 7 Memory and Base Address Map This chapter explains the memory map and the base address map of registers 1 Memory Map 2 Base Address Map 3 Note CODE...

Page 65: ...FFF Reserved 0E00_0000 Work_FLASH 3M Max 0E7F_FFFF Reserved 0E80_0000 0E80_1FFF BACKUP_RAM 8K Backup RAM power supply domain PD4_0 0E80_2000 0E80_3FFF BACKUP_RAM 8K Backup RAM power supply domain PD4_...

Page 66: ...phics Core 5031_0000 503F_FFFF Reserved 5040_0000 504F_FFFF High Performance Bus Matrix 5050_0000 5FFF_FFFF Reserved 6000_0000 7FFF_FFFF Reserved Reserved 8000_0000 8FFF_FFFF HSSPI0_MEMORY DDRHSSPI fo...

Page 67: ...DDR_HSSPI 1 B010_1400 B010_7FFF Reserved Reserved B010_8000 B010_80FF System SRAM SystemSRAM registers 2 B010_8100 B01F_FFFF Reserved Reserved B020_0000 B02F_FFFF Reserved Reserved B030_0000 B030_7FF...

Page 68: ...60_0700 B060_07FF MCU_CONFIG_GROUP Debug register area 51 B060_0800 B060_BFFF MCU_CONFIG_GROUP MODEC 55 B060_C000 B060_FFFF MCU_CONFIG_GROUP HWDT 52 B061_0000 B061_7FFF Reserved Reserved B061_8000 B06...

Page 69: ...0 B471_5FFF Reserved Reserved B471_6000 B471_7FFF Reserved Reserved B471_8000 B471_83FF Common PERI 2 CRC 0 70 B471_8400 B471_87FF Common PERI 2 CRC 1 71 B471_8800 B471_8BFF Common PERI 2 CRC 2 72 B47...

Page 70: ...Reload Timer ch 3 131 B481_1000 B481_7FFF Reserved Reserved B481_8000 B481_FFFF Reserved Reserved B482_0000 B482_03FF Common PERI 0 FRT ch 0 208 B482_0400 B482_07FF Common PERI 0 FRT ch 1 209 B482_080...

Page 71: ...488_13FF Common PERI 1 M F Serial ch 12 188 B488_1400 B488_7FFF Reserved Reserved B488_8000 B488_83FF Common PERI 1 BaseTimer ch 12 100 B488_8400 B488_87FF Common PERI 1 BaseTimer ch 13 101 B488_8800...

Page 72: ...4000 B48C_43FF Common PERI 1 SMC ch 0 286 B48C_4400 B48C_47FF Common PERI 1 SMC ch 1 287 B48C_4800 B48C_4BFF Common PERI 1 SMC ch 2 288 B48C_4C00 B48C_4FFF Common PERI 1 SMC ch 3 289 B48C_5000 B48C_53...

Page 73: ...298 B802_1400 B802_7FFF Reserved Reserved B802_8000 B802_83FF Apps 3 Wave Form Generator Sound System 297 B802_8400 B802_87FF Apps 3 Hyper Bus ch 0 Control Register 302 B802_8800 B802_FFFF Reserved Re...

Page 74: ...or Strongly Ordered should be used MPU attribute Device or Strongly Ordered must be used for areas below to avoid this influence Backup RAM area BACKUP_RAM 0E80_0000 to 0E87_FFFF Peripheral area Peri...

Page 75: ...74 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G CHAPTER 8 IRQ and NMI Map This chapter explains IRQ and NMI map 1 IRQ Map 2 NMI Map CODE IRQMAP S6J3200 E1...

Page 76: ...xternal Interrupt Request ch 0 IRC0_IRQPL6 IRQPL24 IRC0_IRQVA24 25 External Interrupt Request ch 1 IRC0_IRQPL6 IRQPL25 IRC0_IRQVA25 26 External Interrupt Request ch 2 IRC0_IRQPL6 IRQPL26 IRC0_IRQVA26...

Page 77: ...C0_IRQVA72 73 MFS TX ch 4 IRC0_IRQPL18 IRQPL73 IRC0_IRQVA73 74 to 79 Reserved 80 MFS RX ch 8 IRC0_IRQPL20 IRQPL80 IRC0_IRQVA80 81 MFS TX ch 8 IRC0_IRQPL20 IRQPL81 IRC0_IRQVA81 82 MFS RX ch 9 IRC0_IRQP...

Page 78: ...ch 18 IRC0_IRQPL35 IRQPL142 IRC0_IRQVA142 143 Base Timer ch 19 IRC0_IRQPL35 IRQPL143 IRC0_IRQVA143 144 to 151 Reserved 152 Reload Timer ch 0 IRC0_IRQPL38 IRQPL152 IRC0_IRQVA152 153 Reload Timer ch 1...

Page 79: ...f Input Capture 9 IRC0_IRQPL50 IRQPL201 IRC0_IRQVA201 202 IRQ0 of Input Capture 10 IRC0_IRQPL50 IRQPL202 IRC0_IRQVA202 203 IRQ0 of Input Capture 11 IRC0_IRQPL50 IRQPL203 IRC0_IRQVA203 204 to 207 Reser...

Page 80: ...QPL260 IRC0_IRQVA260 261 IRQ1 of Output Compare 5 IRC0_IRQPL65 IRQPL261 IRC0_IRQVA261 262 IRQ1 of Output Compare 6 IRC0_IRQPL65 IRQPL262 IRC0_IRQVA262 263 IRQ1 of Output Compare 7 IRC0_IRQPL65 IRQPL26...

Page 81: ...QPL322 IRC0_IRQVA322 323 MFS ch 3 Error Tx Rx error Status OR ed IRC0_IRQPL80 IRQPL323 IRC0_IRQVA323 324 MFS ch 4 Error Tx Rx error Status OR ed IRC0_IRQPL81 IRQPL324 IRC0_IRQVA324 325 to 327 Reserved...

Page 82: ...RQPL370 IRC0_IRQVA370 371 PCMPWM_UDRN IRC0_IRQPL92 IRQPL371 IRC0_IRQVA371 372 PCMPWM_DMAE IRC0_IRQPL93 IRQPL372 IRC0_IRQVA372 373 AUDIO_DAC_DREQ IRC0_IRQPL93 IRQPL373 IRC0_IRQVA373 374 AUDIO_DAC_OVFL_...

Page 83: ...PL426 IRC0_IRQVA426 427 3D Graphics Core CAEI IRC0_IRQPL106 IRQPL427 IRC0_IRQVA427 428 3D Graphics Core SBEI IRC0_IRQPL107 IRQPL428 IRC0_IRQVA428 429 to 431 Reserved 432 WG_END_IRQ0 IRC0_IRQPL108 IRQP...

Page 84: ...1 NMIPL6 IRC0_NMIVA6 7 SW WDT IRC0_NMIPL1 NMIPL7 IRC0_NMIVA7 8 IRC 2 bit ECC err detection IRC0_NMIPL2 NMIPL8 IRC0_NMIVA8 9 to 10 Reserved 11 Backup RAM 2 bit ECC error detection IRC0_NMIPL2 NMIPL11 I...

Page 85: ...J3200 Series Hardware Manual Document Number 002 04852 Rev G CHAPTER 9 DMA Channel Activation Factors This chapter explains the DMA channel activation factors 1 Factors List 2 Note CODE DMAFACT S6J320...

Page 86: ...9 1 20 Ext IRQ 10 1 21 Ext IRQ 11 1 22 Ext IRQ 12 1 23 Ext IRQ 13 1 24 Ext IRQ 14 1 25 Ext IRQ 15 1 26 to 41 Reserved 42 MFS ch 16 RX 3 43 MFS ch 16 TX 3 44 MFS Ch 17 RX 3 45 MFS Ch 17 TX 3 46 to 47 R...

Page 87: ...8 0 2 90 Base Timer ch 9 0 2 91 Base Timer ch 8 1 2 92 Base Timer ch 9 1 2 93 Base Timer ch 10 0 2 94 Base Timer ch 11 0 2 95 Base Timer ch 10 1 2 96 Base Timer ch 11 1 2 97 Base Timer ch 12 0 2 98 Ba...

Page 88: ...Timer ch 18 1 164 Reload Timer ch 19 1 165 to 176 Reserved 177 Reload Timer ch 32 1 178 Reload Timer ch 33 1 179 Reload Timer ch 34 1 180 Reload Timer ch 35 1 181 to 192 Reserved 193 MFS ch 0 RX 3 194...

Page 89: ...Zero 2 241 FRT ch 8 Match 2 242 FRT ch 8 Zero 2 243 FRT ch 9 Match 2 244 FRT ch 9 Zero 2 245 FRT ch 10 Match 2 246 FRT ch 10 Zero 2 247 FRT ch 11 Match 2 248 FRT ch 11 Zero 2 249 to 256 Reserved 257 I...

Page 90: ...h 3 1 2 297 OCU pair ch 4 0 2 298 OCU pair ch 4 1 2 299 OCU pair ch 5 0 2 300 OCU pair ch 5 1 2 301 OCU pair ch 6 0 2 302 OCU pair ch 6 1 2 303 OCU pair ch 7 0 2 304 OCU pair ch 7 1 2 305 OCU pair ch...

Page 91: ...leared the interrupt factor flag of peripheral function by acceptance of DMA transfer request Interrupt Enable 1 Not cleared Unnecessary 1 2 Cleared Necessary 3 2 Not cleared Necessary 1 Necessary to...

Page 92: ...S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 91 CHAPTER 10 Port Description This chapter explains port functions 1 Port Description List 2 Remark CODE PORT_DESCRIPTION S6J3200 E1...

Page 93: ...203 VSS_LVDS_Tx LVDS Tx GND 15 26 15 26 AVCC3_DAC Audio DAC power supply pin 6 6 AVCC3_LVDS_PLL LVDS PLL power supply pin 13 13 AVSS_LVDS_PLL LVDS PLL GND 12 12 AVCC5 A D converter analog power supply...

Page 94: ...Analog 9 input pin 97 101 AN10 ADC Analog 10 input pin 98 102 AN11 ADC Analog 11 input pin 99 103 AN12 ADC Analog 12 input pin 100 104 AN13 ADC Analog 13 input pin 101 105 AN14 ADC Analog 14 input pin...

Page 95: ...ssion data 5 output pin 162 166 168 174 TX6 CAN transmission data 6 output pin 168 170 176 RX0 CAN reception data 0 input pin 99 103 RX1 CAN reception data 1 input pin 101 153 105 159 RX5 CAN receptio...

Page 96: ...153 159 MFS0_CS2 Multi function serial ch 0 chip select 2 pin 154 160 MFS0_CS3 Multi function serial ch 0 chip select 3 pin 152 158 MFS2_CS0 Multi function serial ch 2 chip select 0 pin 149 155 MFS2_...

Page 97: ...Multi function serial ch 17 serial data input pin 92 95 SOT0 Multi function serial ch 0 serial data output pin 37 90 37 93 SOT1 Multi function serial ch 1 serial data output pin 82 93 84 97 SOT2 Mult...

Page 98: ...154 173 183 PPG3_TOUT2 Base timer 7 output pin 32 46 149 166 176 32 48 155 174 184 PPG4_TOUT0 Base timer 8 output pin 33 47 150 167 177 33 49 92 156 175 185 PPG4_TOUT2 Base timer 9 output pin 48 84 90...

Page 99: ...4 PWM1M5 SMC ch 5 output pin 152 158 PWM1P0 SMC ch 0 output pin 127 133 PWM1P1 SMC ch 1 output pin 131 137 PWM1P2 SMC ch 2 output pin 137 143 PWM1P3 SMC ch 3 output pin 141 147 PWM1P4 SMC ch 4 output...

Page 100: ...77 96 124 160 189 OCU6_OTD1 Output compare 6 ch 1 output pin 54 77 93 127 186 56 79 97 133 194 OCU7_OTD0 Output compare 7 ch 0 output pin 55 76 94 128 187 57 78 98 134 195 OCU7_OTD1 Output compare 7...

Page 101: ...5_IN1 Input Capture 5 ch 1 input pin 50 72 92 153 180 52 74 95 123 159 188 ICU6_IN0 Input Capture 6 ch 0 input pin 51 75 154 181 53 77 96 124 160 189 ICU6_IN1 Input Capture 6 ch 1 input pin 54 77 93 1...

Page 102: ...pin 50 52 I2S1_ECLK I2S external clock ch 1 input pin 56 58 I2S0_SCK I2S continuous serial clock ch 0 pin 55 57 I2S1_SCK I2S continuous serial clock ch 1 pin 59 61 I2S0_SD I2S serial data ch 0 pin 51...

Page 103: ...2 171 TOT33 Reload timer ch 33 output pin 54 165 56 173 TOT34 Reload timer ch 34 output pin 56 167 58 175 TOT35 Reload timer ch 35 output pin 58 118 60 122 AIN8 Up Down counter AIN input pin ch 8 190...

Page 104: ...data output pin 16 16 Described as TXOUT3P in FPD Link Converter G_SCLK0 Graphic HS SPI clock output pin 72 74 G_SDATA0_0 Graphic HS SPI0 data 0 pin 75 77 G_SDATA0_1 Graphic HS SPI0 data 1 pin 77 79 G...

Page 105: ...data 2 pin 76 78 M_SDATA1_3 MCU HS SPI1 data 3 pin 79 81 M_SSEL0 MCU HS SPI select 0 output pin 69 71 M_SSEL1 MCU HS SPI select 1 output pin 78 80 M_CK_0 MCU Hyper Bus clock output pin 63 65 M_CS 1_0...

Page 106: ...egment Duty Static Output Pin 167 175 SEG26 LCDC Segment Duty Static Output Pin 166 174 SEG27 LCDC Segment Duty Static Output Pin 165 173 SEG28 LCDC Segment Duty Static Output Pin 164 172 SEG29 LCDC S...

Page 107: ...3 33 45 DSP0_DATA1_5 Display 0 Data output pin 45 47 DSP0_DATA1_6 Display 0 Data output pin 47 49 DSP0_DATA1_7 Display 0 Data output pin 49 51 DSP0_DATA1_8 Display 0 Data output pin 51 53 DSP0_DATA1_9...

Page 108: ...pin 187 195 DSP1_DATA0_8 Display 1 Data output pin 181 189 DSP1_DATA0_9 Display 1 Data output pin 179 187 DSP1_DATA0_10 Display 1 Data output pin 177 185 DSP1_DATA0_11 Display 1 Data output pin 175 1...

Page 109: ...e 0 Data input pin 82 84 CAP0_DATA25 Video Capture 0 Data input pin 83 85 CAP0_DATA32 Video Capture 0 Data input pin 56 57 58 59 CAP0_DATA33 Video Capture 0 Data input pin 58 60 CAP0_DATA34 Video Capt...

Page 110: ...l Purpose I O port 169 177 P2_19 General Purpose I O port 159 165 P2_22 General Purpose I O port 89 91 P2_24 General Purpose I O port 92 P2_25 General Purpose I O port 90 93 P2_26 General Purpose I O...

Page 111: ...ose I O port 141 147 P4_02 General Purpose I O port 142 148 P4_03 General Purpose I O port 143 149 P4_04 General Purpose I O port 144 150 P4_05 General Purpose I O port 147 153 P4_06 General Purpose I...

Page 112: ..._19 General Purpose I O port 202 210 P5_20 General Purpose I O port 203 211 P5_21 General Purpose I O port 31 31 P5_22 General Purpose I O port 60 62 P5_27 General Purpose I O port 34 34 P5_28 General...

Page 113: ...ment Number 002 04852 Rev G CHAPTER 11 Port Configuration This chapter explains the port configuration 1 Overview 2 Configuration and Block Diagram 3 Operation 4 Registers 5 Configuration Procedure 6...

Page 114: ...are multiplexed implemented in a pin and the assignment to a pin is particular for the product A port configuration is to determine which function and which input output direction is applied to a port...

Page 115: ...SSMODE PowerDomain 1 Latch Latch Latch PowerDomain2 PowerDomain2 Latch Latch PowerDomain2 Latch Latch Latch Latch Latch Latch Latch PowerDomain 1 HOLDIO_PD2 HOLDIO_PD6 EN EN EN EN EN EN EN Note Latch...

Page 116: ...or a resource inputs from the other resource has its RIC_RESIN register to configure resource input configuration Register Offset Resource RESSE L 3 0 PORTS EL 3 0 Source for Resource Input 0 1 2 3 4...

Page 117: ...2 13 14 15 RIC_RE SIN094 0x00BC SDA10 RESSE L 0 7 80ns noise filter disable 80ns noise filter enable RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN107 0x00D6 SCL12 RESSE L 0 7 80ns noise filter di...

Page 118: ...6 7 8 9 10 11 12 13 14 15 RIC_RE SIN002 0x0004 SCL16 RESSE L 0 7 80ns noise filter disable 80ns noise filter enable RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN003 0x0006 SDA16 RESSE L 0 7 80ns...

Page 119: ...2 SCL17 RESSE L 0 7 80ns noise filter disable 80ns noise filter enable RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN010 0x0014 SDA17 RESSE L 0 7 80ns noise filter disable 80ns noise filter enable...

Page 120: ...CK0 RESSE L 0 7 RESSE L 8 15 PORTS EL 0 7 P2_26 P5_31 PORTS EL 8 15 RIC_RE SIN023 0x002E SCL0 RESSE L 0 7 80ns noise filter disable 80ns noise filter enable RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC...

Page 121: ...8 SIN1 RESSE L 0 7 RESSE L 8 15 PORTS EL 0 7 set 1 P2_31 P0_28 PORTS EL 8 15 RIC_RE SIN029 0x003A SCK1 RESSE L 0 7 RESSE L 8 15 PORTS EL 0 7 set 1 P2_30 P0_27 PORTS EL 8 15 RIC_RE SIN030 0x003C SCL1 R...

Page 122: ...IN032 0x0040 MFS1_TRIG GER RESSE L 0 7 TOT0 TOT1 TOT2 TOT3 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN039 0x004E MFS2_TRIG GER RESSE L 0 7 TOT0 TOT1 TOT2 TOT3 RESSE L 8 15 PORTS EL 0 7 PORTS EL...

Page 123: ...14 15 RIC_RE SIN077 0x009A SIN8 RESSE L 0 7 RESSE L 8 15 PORTS EL 0 7 set 1 P5_04 P3_05 PORTS EL 8 15 RIC_RE SIN078 0x009C SCK8 RESSE L 0 7 RESSE L 8 15 PORTS EL 0 7 set 1 P5_03 P3_04 PORTS EL 8 15 RI...

Page 124: ...4 15 RIC_RE SIN085 0x00AA SCK9 RESSE L 0 7 RESSE L 8 15 PORTS EL 0 7 set 1 P5_07 P3_08 PORTS EL 8 15 RIC_RE SIN088 0x00B0 MFS9_TRIG GER RESSE L 0 7 TOT16 TOT17 TOT18 TOT19 RESSE L 8 15 PORTS EL 0 7 PO...

Page 125: ...N095 0x00BE MFS10_TRI GGER RESSE L 0 7 TOT16 TOT17 TOT18 TOT19 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN098 0x00C4 SIN11 RESSE L 0 7 RESSE L 8 15 PORTS EL 0 7 set 1 P5_16 P3_17 P4_28 PORTS EL...

Page 126: ...TRI GGER RESSE L 0 7 TOT16 TOT17 TOT18 TOT19 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN133 0x010A RX5 RESSE L 0 7 PORT_P IN MCAN5_ PIN_AN D_TX RESSE L 8 15 PORTS EL 0 7 set 1 P3_08 PORTS EL 8...

Page 127: ...L 0 7 PORT_P IN MCAN1_ PIN_AN D_TX RESSE L 8 15 PORTS EL 0 7 set 1 P3_05 P4_11 PORTS EL 8 15 RIC_RE SIN141 0x011A TIN48 RESSE L 0 7 PORT_P IN TOT49 RLT49_U FSET RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15...

Page 128: ...TOT2 PPG1_T OUT0 RESSE L 8 15 PORTS EL 0 7 P2_29 P5_30 PORTS EL 8 15 RIC_RE SIN146 0x0124 TIN2 RESSE L 0 7 PORT_P IN TOT1 RLT1_U FSET TOT3 PPG2_T OUT0 RESSE L 8 15 PORTS EL 0 7 P6_00 P2_30 PORTS EL 8...

Page 129: ...SET TOT18 PPG7_T OUT0 RESSE L 8 15 PORTS EL 0 7 P0_05 P3_06 PORTS EL 8 15 RIC_RE SIN162 0x0144 TIN18 RESSE L 0 7 PORT_P IN TOT17 RLT17_U FSET TOT19 PPG8_T OUT0 RESSE L 8 15 PORTS EL 0 7 P0_07 P3_09 PO...

Page 130: ...2 RLT32_U FSET TOT34 RESSE L 8 15 PORTS EL 0 7 P0_13 P3_15 PORTS EL 8 15 RIC_RE SIN178 0x0164 TIN34 RESSE L 0 7 PORT_P IN TOT33 RLT33_U FSET TOT35 RESSE L 8 15 PORTS EL 0 7 P0_15 P3_17 PORTS EL 8 15 R...

Page 131: ...PORTS EL 0 7 P0_00 P0_16 P0_26 P2_17 P3_01 P3_17 P4_01 PORTS EL 8 15 P5_01 P5_17 RIC_RE SIN194 0x0184 EINT2 RESSE L 0 7 RESSE L 8 15 PORTS EL 0 7 P0_01 P0_17 P0_27 P3_02 P3_18 P4_02 PORTS EL 8 15 P5_...

Page 132: ...SE L 0 7 RESSE L 8 15 PORTS EL 0 7 P0_04 P0_30 P3_05 P3_21 P4_05 PORTS EL 8 15 P5_05 RIC_RE SIN198 0x018C EINT6 RESSE L 0 7 RESSE L 8 15 PORTS EL 0 7 P0_05 P0_31 P2_22 P3_06 P3_22 P4_06 PORTS EL 8 15...

Page 133: ...S EL 0 7 P0_08 P1_02 P2_25 P3_09 P3_25 P4_09 P4_25 PORTS EL 8 15 P5_09 RIC_RE SIN202 0x0194 EINT10 RESSE L 0 7 RESSE L 8 15 PORTS EL 0 7 P0_09 P1_03 P2_26 P3_10 P3_26 P4_10 P4_26 PORTS EL 8 15 P5_10 R...

Page 134: ...8 15 PORTS EL 0 7 P0_12 P1_06 P2_29 P3_13 P3_29 P4_29 PORTS EL 8 15 P5_13 P5_29 RIC_RE SIN206 0x019C EINT14 RESSE L 0 7 RESSE L 8 15 PORTS EL 0 7 P0_13 P1_07 P2_30 P3_14 P3_30 P4_30 PORTS EL 8 15 P5_...

Page 135: ...1_TEXT RESSE L 0 7 PORT_P IN TOT0 TOT2 PPG1_T OUT2 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN226 0x01C4 FRT2_TEXT RESSE L 0 7 PORT_P IN TOT0 TOT3 PPG2_T OUT2 RESSE L 8 15 PORTS EL 0 7 PORTS EL...

Page 136: ...ESSE L 0 7 PORT_P IN TOT0 TOT3 PPG5_T OUT2 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN230 0x01CC FRT6_TEXT RESSE L 0 7 PORT_P IN TOT0 TOT1 PPG0_T OUT2 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RI...

Page 137: ...13 14 15 RIC_RE SIN233 0x01D2 FRT9_TEXT RESSE L 0 7 PORT_P IN RLT3_U FSET RLT17_U FSET PPG7_T OUT2 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN234 0x01D4 FRT10_TEX T RESSE L 0 7 PORT_P IN RLT3_U...

Page 138: ...8 9 10 11 12 13 14 15 RIC_RE SIN240 0x01E0 OCU pair Ch 0 0 RESSE L 0 7 FRT Ch0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 OCU pair Ch 0 1 RESSE L 0 7 FRT Ch0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_...

Page 139: ...11 12 13 14 15 RIC_RE SIN243 0x01E6 OCU pair Ch 1 0 RESSE L 0 7 FRT Ch1 FRT Ch0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 OCU pair Ch 1 1 RESSE L 0 7 FRT Ch1 FRT Ch0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8...

Page 140: ...11 12 13 14 15 RIC_RE SIN246 0x01EC OCU pair Ch 2 0 RESSE L 0 7 FRT Ch2 FRT Ch0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 OCU pair Ch 2 1 RESSE L 0 7 FRT Ch2 FRT Ch0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8...

Page 141: ...IC_RE SIN249 0x01F2 OCU pair Ch 3 0 RESSE L 0 7 FRT Ch3 FRT Ch0 FRT Ch1 FRT Ch2 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 OCU pair Ch 3 1 RESSE L 0 7 FRT Ch3 FRT Ch0 FRT Ch1 FRT Ch2 RESSE L 8 15 PORTS E...

Page 142: ...8 9 10 11 12 13 14 15 RIC_RE SIN252 0x01F8 OCU pair Ch 4 0 RESSE L 0 7 FRT Ch4 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 OCU pair Ch 4 1 RESSE L 0 7 FRT Ch4 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_...

Page 143: ...3 14 15 RIC_RE SIN255 0x01FE OCU pair Ch 5 0 RESSE L 0 7 FRT Ch5 FRT Ch4 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 OCU pair Ch 5 1 RESSE L 0 7 FRT Ch5 FRT Ch4 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 POR...

Page 144: ...11 12 13 14 15 RIC_RE SIN258 0x0204 OCU pair Ch 6 0 RESSE L 0 7 FRT Ch6 FRT Ch4 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 OCU pair Ch 6 1 RESSE L 0 7 FRT Ch6 FRT Ch4 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8...

Page 145: ...IC_RE SIN261 0x020A OCU pair Ch 7 0 RESSE L 0 7 FRT Ch7 FRT Ch4 FRT Ch5 FRT Ch6 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 OCU pair Ch 7 1 RESSE L 0 7 FRT Ch7 FRT Ch4 FRT Ch5 FRT Ch6 RESSE L 8 15 PORTS E...

Page 146: ...8 9 10 11 12 13 14 15 RIC_RE SIN264 0x0210 OCU pair Ch 8 0 RESSE L 0 7 FRT Ch8 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 OCU pair Ch 8 1 RESSE L 0 7 FRT Ch8 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_...

Page 147: ...11 12 13 14 15 RIC_RE SIN267 0x0216 OCU pair Ch 9 0 RESSE L 0 7 FRT Ch9 FRT Ch8 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 OCU pair Ch 9 1 RESSE L 0 7 FRT Ch9 FRT Ch8 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8...

Page 148: ...12 13 14 15 RIC_RE SIN270 0x021C OCU pair Ch 10 0 RESSE L 0 7 FRT Ch10 FRT Ch8 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 OCU pair Ch 10 1 RESSE L 0 7 FRT Ch10 FRT Ch8 RESSE L 8 15 PORTS EL 0 7 PORTS EL...

Page 149: ...E SIN273 0x0222 OCU pair Ch 11 0 RESSE L 0 7 FRT Ch11 FRT Ch8 FRT Ch9 FRT Ch10 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 OCU pair Ch 11 1 RESSE L 0 7 FRT Ch11 FRT Ch8 FRT Ch9 FRT Ch10 RESSE L 8 15 PORTS...

Page 150: ...ICU0_IN0 RESSE L 0 7 PORT_P IN MFS0_L SYN RESSE L 8 15 PORTS EL 0 7 P6_00 P2_16 P3_08 PORTS EL 8 15 P4_00 P5_16 RIC_RE SIN289 0x0242 ICU0_IN1 RESSE L 0 7 PORT_P IN MFS1_L SYN RESSE L 8 15 PORTS EL 0...

Page 151: ...0 RESSE L 0 7 PORT_P IN MFS2_L SYN RESSE L 8 15 PORTS EL 0 7 P0_01 P3_10 PORTS EL 8 15 P4_02 P4_26 P5_18 RIC_RE SIN292 0x0248 ICU1_IN1 RESSE L 0 7 PORT_P IN MFS3_L SYN RESSE L 8 15 PORTS EL 0 7 set 1...

Page 152: ...024C ICU2_IN0 RESSE L 0 7 PORT_P IN MFS4_L SYN RESSE L 8 15 PORTS EL 0 7 P0_03 P3_12 PORTS EL 8 15 P4_04 P4_28 P5_20 RIC_RE SIN295 0x024E ICU2_IN1 RESSE L 0 7 PORT_P IN RESSE L 8 15 PORTS EL 0 7 set 1...

Page 153: ...RESSE L 0 7 PORT_P IN RESSE L 8 15 PORTS EL 0 7 P0_05 P2_22 P3_14 PORTS EL 8 15 P4_06 P4_30 RIC_RE SIN298 0x0254 ICU3_IN1 RESSE L 0 7 PORT_P IN RESSE L 8 15 PORTS EL 0 7 set 1 P0_06 P0_18 P3_15 PORTS...

Page 154: ...0 0x0258 ICU4_IN0 RESSE L 0 7 PORT_P IN RESSE L 8 15 PORTS EL 0 7 P0_07 P0_19 P2_24 P3_16 PORTS EL 8 15 P4_08 P5_00 RIC_RE SIN301 0x025A ICU4_IN1 RESSE L 0 7 PORT_P IN RESSE L 8 15 PORTS EL 0 7 set 1...

Page 155: ...25E ICU5_IN0 RESSE L 0 7 PORT_P IN RESSE L 8 15 PORTS EL 0 7 P0_09 P2_26 P3_18 PORTS EL 8 15 P4_10 P5_02 RIC_RE SIN304 0x0260 ICU5_IN1 RESSE L 0 7 PORT_P IN RESSE L 8 15 PORTS EL 0 7 set 1 P0_10 P0_30...

Page 156: ...264 ICU6_IN0 RESSE L 0 7 PORT_P IN RESSE L 8 15 PORTS EL 0 7 P0_11 P0_31 P2_28 P3_20 PORTS EL 8 15 P4_12 P5_04 RIC_RE SIN307 0x0266 ICU6_IN1 RESSE L 0 7 PORT_P IN RESSE L 8 15 PORTS EL 0 7 set 1 P0_12...

Page 157: ...RESSE L 0 7 PORT_P IN RESSE L 8 15 PORTS EL 0 7 P0_13 P1_01 P2_30 P3_22 PORTS EL 8 15 P5_06 RIC_RE SIN310 0x026C ICU7_IN1 RESSE L 0 7 PORT_P IN RESSE L 8 15 PORTS EL 0 7 set 1 P0_14 P1_02 P2_31 P3_23...

Page 158: ...270 ICU8_IN0 RESSE L 0 7 PORT_P IN MFS8_L SYN RESSE L 8 15 PORTS EL 0 7 P0_15 P1_03 P3_00 P3_24 PORTS EL 8 15 P5_08 RIC_RE SIN313 0x0272 ICU8_IN1 RESSE L 0 7 PORT_P IN MFS9_L SYN RESSE L 8 15 PORTS EL...

Page 159: ...RESSE L 0 7 PORT_P IN MFS10_ LSYN RESSE L 8 15 PORTS EL 0 7 P0_17 P1_05 P3_02 P3_26 PORTS EL 8 15 P5_10 RIC_RE SIN316 0x0278 ICU9_IN1 RESSE L 0 7 PORT_P IN MFS11_ LSYN RESSE L 8 15 PORTS EL 0 7 set 1...

Page 160: ..._IN0 RESSE L 0 7 PORT_P IN MFS12_ LSYN RESSE L 8 15 PORTS EL 0 7 P5_22 P1_07 P3_04 P3_28 PORTS EL 8 15 P5_12 P5_28 RIC_RE SIN319 0x027E ICU10_IN1 RESSE L 0 7 PORT_P IN RESSE L 8 15 PORTS EL 0 7 set 1...

Page 161: ...RESSE L 0 7 PORT_P IN RESSE L 8 15 PORTS EL 0 7 set 1 P1_09 P3_06 P3_30 PORTS EL 8 15 P5_14 P5_30 RIC_RE SIN322 0x0284 ICU11_IN1 RESSE L 0 7 PORT_P IN RESSE L 8 15 PORTS EL 0 7 P5_31 P3_07 P3_31 PORTS...

Page 162: ...8 RESSE L 0 7 PORT_P IN TOT16 RESSE L 8 15 PORTS EL 0 7 P2_24 P5_09 PORTS EL 8 15 RIC_RE SIN361 0x02D2 BIN8 RESSE L 0 7 PORT_P IN TOT17 RESSE L 8 15 PORTS EL 0 7 P2_25 P5_10 PORTS EL 8 15 RIC_RE SIN36...

Page 163: ...PORT_P IN TOT18 RESSE L 8 15 PORTS EL 0 7 P2_30 P5_13 PORTS EL 8 15 RIC_RE SIN365 0x02DA ZIN9 RESSE L 0 7 PORT_P IN TOT19 PPG6_T OUT0 PPG6_T OUT2 PPG7_T OUT0 RESSE L 8 15 PORTS EL 0 7 P2_31 P5_14 POR...

Page 164: ...C_RE SIN386 0x0304 PPG0_TIN3 RESSE L 0 7 set 0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN387 0x0306 PPG1_TIN1 RESSE L 0 7 PORT_P IN TOT0 RLT0_U FSET TOT2 RLT2_U FSET FRT3_M TSF OCU3_O TD0 RESS...

Page 165: ...ESSE L 0 7 PORT_P IN TOT0 RLT0_U FSET TOT3 RLT3_U FSET FRT3_M TSF OCU3_O TD0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN391 0x030E PPG2_TIN2 RESSE L 0 7 set 0 RESSE L 8 15 PORTS EL 0 7 PORTS EL...

Page 166: ...C_RE SIN394 0x0314 PPG3_TIN2 RESSE L 0 7 set 0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN395 0x0316 PPG3_TIN3 RESSE L 0 7 set 0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN396 0x0318 PPG...

Page 167: ...C_RE SIN398 0x031C PPG4_TIN3 RESSE L 0 7 set 0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN399 0x031E PPG5_TIN1 RESSE L 0 7 PORT_P IN TOT0 RLT0_U FSET TOT3 RLT3_U FSET FRT3_M TSF OCU3_O TD0 RESS...

Page 168: ...0 7 PORT_P IN TOT16 RLT16_U FSET TOT17 RLT17_U FSET FRT11_ MTSF OCU11_ OTD0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN403 0x0326 PPG6_TIN2 RESSE L 0 7 set 0 RESSE L 8 15 PORTS EL 0 7 PORTS EL...

Page 169: ...E SIN406 0x032C PPG7_TIN2 RESSE L 0 7 set 0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN407 0x032E PPG7_TIN3 RESSE L 0 7 set 0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN408 0x0330 PPG8_T...

Page 170: ...E SIN410 0x0334 PPG8_TIN3 RESSE L 0 7 set 0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN411 0x0336 PPG9_TIN1 RESSE L 0 7 PORT_P IN TOT16 RLT16_U FSET TOT17 RLT17_U FSET FRT11_ MTSF OCU11_ OTD0 R...

Page 171: ...0 7 PORT_P IN TOT16 RLT16_U FSET TOT18 RLT18_U FSET FRT11_ MTSF OCU11_ OTD0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN415 0x033E PPG10_TIN2 RESSE L 0 7 set 0 RESSE L 8 15 PORTS EL 0 7 PORTS EL...

Page 172: ...S EL 0 7 PORTS EL 8 15 RIC_RE SIN419 0x0346 PPG11_TIN3 RESSE L 0 7 set 0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN438 0x036C ADC12B_HW TRG0 RESSE L 0 7 PORT_P IN RLT0_U FSET RLT1_U FSET OCU0_...

Page 173: ...L 0 7 PORTS EL 8 15 RIC_RE SIN441 0x0372 ADC12B_HW TRG3 RESSE L 0 7 PORT_P IN RLT3_U FSET RLT16_U FSET OCU3_O TD0 OCU4_O TD0 BT1_AD TOUT2 BT3_AD TOUT0 BT5_AD TOUT0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8...

Page 174: ...L 0 7 PORTS EL 8 15 RIC_RE SIN445 0x037A ADC12B_HW TRG7 RESSE L 0 7 PORT_P IN RLT19_U FSET RLT32_U FSET OCU7_O TD0 OCU8_O TD0 BT3_AD TOUT2 BT5_AD TOUT0 BT7_AD TOUT0 RESSE L 8 15 PORTS EL 0 7 PORTS EL...

Page 175: ...EL 0 7 PORTS EL 8 15 RIC_RE SIN449 0x0382 ADC12B_HW TRG11 RESSE L 0 7 PORT_P IN RLT35_U FSET RLT0_U FSET OCU11_ OTD0 OCU0_O TD0 BT5_AD TOUT2 BT7_AD TOUT0 BT9_AD TOUT0 RESSE L 8 15 PORTS EL 0 7 PORTS...

Page 176: ...0 7 PORTS EL 8 15 RIC_RE SIN453 0x038A ADC12B_HW TRG15 RESSE L 0 7 PORT_P IN RLT3_U FSET RLT17_U FSET OCU3_O TD0 OCU5_O TD0 BT7_AD TOUT2 BT9_AD TOUT0 BT11_A DTOUT0 RESSE L 8 15 PORTS EL 0 7 PORTS EL...

Page 177: ...7 PORTS EL 8 15 RIC_RE SIN457 0x0392 ADC12B_HW TRG19 RESSE L 0 7 PORT_P IN RLT19_U FSET RLT33_U FSET OCU7_O TD0 OCU9_O TD0 BT9_AD TOUT2 BT11_A DTOUT0 BT1_AD TOUT0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8...

Page 178: ...EL 0 7 PORTS EL 8 15 RIC_RE SIN461 0x039A ADC12B_HW TRG23 RESSE L 0 7 PORT_P IN RLT35_U FSET RLT1_U FSET OCU11_ OTD0 OCU1_O TD0 BT11_A DTOUT2 BT1_AD TOUT0 BT3_AD TOUT0 RESSE L 8 15 PORTS EL 0 7 PORTS...

Page 179: ...L 0 7 PORTS EL 8 15 RIC_RE SIN465 0x03A2 ADC12B_HW TRG27 RESSE L 0 7 PORT_P IN RLT3_U FSET RLT18_U FSET OCU3_O TD0 OCU6_O TD0 BT1_AD TOUT2 BT2_AD TOUT0 BT4_AD TOUT0 RESSE L 8 15 PORTS EL 0 7 PORTS EL...

Page 180: ...0 7 PORTS EL 8 15 RIC_RE SIN469 0x03AA ADC12B_HW TRG31 RESSE L 0 7 PORT_P IN RLT19_U FSET RLT34_U FSET OCU7_O TD0 OCU10_ OTD0 BT3_AD TOUT2 BT4_AD TOUT0 BT6_AD TOUT0 RESSE L 8 15 PORTS EL 0 7 PORTS EL...

Page 181: ...EL 0 7 PORTS EL 8 15 RIC_RE SIN473 0x03B2 ADC12B_HW TRG35 RESSE L 0 7 PORT_P IN RLT35_U FSET RLT2_U FSET OCU11_ OTD0 OCU2_O TD0 BT5_AD TOUT2 BT6_AD TOUT0 BT8_AD TOUT0 RESSE L 8 15 PORTS EL 0 7 PORTS E...

Page 182: ...0 7 PORTS EL 8 15 RIC_RE SIN477 0x03BA ADC12B_HW TRG39 RESSE L 0 7 PORT_P IN RLT3_U FSET RLT19_U FSET OCU3_O TD0 OCU7_O TD0 BT7_AD TOUT2 BT8_AD TOUT0 BT10_A DTOUT0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8...

Page 183: ...0 7 PORTS EL 8 15 RIC_RE SIN481 0x03C2 ADC12B_HW TRG43 RESSE L 0 7 PORT_P IN RLT19_U FSET RLT35_U FSET OCU7_O TD0 OCU11_ OTD0 BT9_AD TOUT2 BT10_A DTOUT0 BT0_AD TOUT0 RESSE L 8 15 PORTS EL 0 7 PORTS E...

Page 184: ...EL 0 7 PORTS EL 8 15 RIC_RE SIN485 0x03CA ADC12B_HW TRG47 RESSE L 0 7 PORT_P IN RLT35_U FSET RLT3_U FSET OCU11_ OTD0 OCU3_O TD0 BT11_A DTOUT2 BT0_AD TOUT0 BT2_AD TOUT0 RESSE L 8 15 PORTS EL 0 7 PORTS...

Page 185: ...0 7 PORTS EL 8 15 RIC_RE SIN489 0x03D2 ADC12B_HW TRG51 RESSE L 0 7 PORT_P IN RLT3_U FSET RLT32_U FSET OCU3_O TD0 OCU8_O TD0 BT1_AD TOUT2 BT5_AD TOUT2 BT6_AD TOUT2 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8...

Page 186: ...EL 0 7 PORTS EL 8 15 RIC_RE SIN493 0x03DA ADC12B_HW TRG55 RESSE L 0 7 PORT_P IN RLT19_U FSET RLT0_U FSET OCU7_O TD0 OCU0_O TD0 BT3_AD TOUT2 BT7_AD TOUT2 BT8_AD TOUT2 RESSE L 8 15 PORTS EL 0 7 PORTS E...

Page 187: ...0 7 PORTS EL 8 15 RIC_RE SIN497 0x03E2 ADC12B_HW TRG59 RESSE L 0 7 PORT_P IN RLT35_U FSET RLT16_U FSET OCU11_ OTD0 OCU4_O TD0 BT5_AD TOUT2 BT9_AD TOUT2 BT10_A DTOUT2 RESSE L 8 15 PORTS EL 0 7 PORTS EL...

Page 188: ...2_O TD0 OCU8_O TD0 BT7_AD TOUT0 BT11_A DTOUT0 BT0_AD TOUT0 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN501 0x03EA ADC12B_HW TRG63 RESSE L 0 7 PORT_P IN RLT3_U FSET RLT33_U FSET OCU3_O TD0 OCU9_O...

Page 189: ...1 12 13 14 15 RIC_RE SIN521 0x0412 CAP0_MOD E0 RESSE L 0 7 set 0 set 1 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8 15 RIC_RE SIN522 0x0414 CAP0_MOD E1 RESSE L 0 7 set 0 set 1 RESSE L 8 15 PORTS EL 0 7 PORTS...

Page 190: ...15 RIC_RE SIN531 0x0426 COL RESSE L 0 7 RESSE L 8 15 PORTS EL 0 7 set 1 P0_16 P0_02 PORTS EL 8 15 RIC_RE SIN542 0x043C ECLK0 RESSE L 0 7 PORT_P IN SYSC1_ CLK_CD 4 RESSE L 8 15 PORTS EL 0 7 PORTS EL 8...

Page 191: ...13 14 15 RIC_RE SIN559 0x045E CAP0_DATA 12 RESSE L 0 7 RESSE L 8 15 PORTS EL 0 7 P0_03 P0_05 PORTS EL 8 15 RIC_RE SIN560 0x0460 CAP0_DATA 13 RESSE L 0 7 RESSE L 8 15 PORTS EL 0 7 P0_04 P0_06 PORTS EL...

Page 192: ...1 is inputted OCUx_MODn is described as MODn pin in Traveo Platform manual Use external interrupt EINTn n 0 to 15 port which is in VCC5 or VCC53 power supply area in order to wake up from PSS shutdown...

Page 193: ...SP0_DA TA_D4 TOT16 OCU1_OTD1 PPG1_TO UT2 PPC_PCF GR003 0x0006 P0_03 GPIO_POD R0 POD 3 DSP0_DAT A1_4 GFXCOR E_RSDS_ INACTIVE OCU2_OTD0 PPG2_TO UT0 PPC_PCF GR004 0x0008 P0_04 GPIO_POD R0 POD 4 DSP0_DAT...

Page 194: ...SP0_CT RL2 OCU8_OTD0 PPG8_TO UT0 DQ7_2 PPC_PCF GR016 0x0020 P0_16 GPIO_POD R0 POD 16 DSP0_DAT A0_11 DSP0_DA TA_D11 I2S1_WS TOT35 OCU8_OTD1 PPG8_TO UT2 DSP0_CL K PPC_PCF GR017 0x0022 P0_17 GPIO_POD R0...

Page 195: ...O_POD R1 POD 4 M_SSEL0 G_SSEL1 DQ0_0 1 OCU8_OTD1 PPG8_TO UT2 PPC_PCF GR105 0x004A P1_05 GPIO_POD R1 POD 5 M_SDATA0 _0 G_SDATA 1_0 DQ3_0 1 OCU9_OTD0 PPG9_TO UT0 PPC_PCF GR106 0x004C P1_06 GPIO_POD R1 P...

Page 196: ...PPG6_TO UT0 PPC_PCF GR229 0x00BA P2_29 GPIO_POD R2 POD 29 SGO2 SOT1 OCU6_OTD1 PPG6_TO UT2 PPC_PCF GR230 0x00BC P2_30 GPIO_POD R2 POD 30 SGA3 SCK1 OCU7_OTD0 PPG7_TO UT0 PPC_PCF GR231 0x00BE P2_31 GPIO...

Page 197: ...0 PPC_PCF GR311 0x00D6 P3_11 GPIO_POD R3 POD 11 TX6 OCU1_OTD1 PPG1_TO UT2 PPC_PCF GR312 0x00D8 P3_12 GPIO_POD R3 POD 12 SGO0 TOT32 SOT10 MFS8_CS 0 OCU2_OTD0 PPG2_TO UT0 PPC_PCF GR313 0x00DA P3_13 GPIO...

Page 198: ...PWM2M0 BN0 BL0 OCU8_OTD0 PPG8_TO UT0 PPC_PCF GR325 0x00F2 P3_25 GPIO_POD R3 POD 25 PWM1P1 AP1 AH1 OCU8_OTD1 PPG8_TO UT2 PPC_PCF GR326 0x00F4 P3_26 GPIO_POD R3 POD 26 PWM1M1 AN1 AL1 OCU9_OTD0 PPG9_TO...

Page 199: ...010E P4_07 GPIO_POD R4 POD 7 PWM2P4 SCK3 MFS2_CS 0 OCU3_OTD1 PPG3_TO UT2 PPC_PCF GR408 0x0110 P4_08 GPIO_POD R4 POD 8 PWM2M4 MFS2_CS 1 OCU4_OTD0 PPG4_TO UT0 PPC_PCF GR409 0x0112 P4_09 GPIO_POD R4 POD...

Page 200: ...SP1_DAT A0_10 BL0 OCU4_OTD0 PPG4_TO UT0 PPC_PCF GR501 0x0142 P5_01 GPIO_POD R5 POD 1 DSP1_DAT A1_9 AH1 OCU4_OTD1 PPG4_TO UT2 PPC_PCF GR502 0x0144 P5_02 GPIO_POD R5 POD 2 DSP1_DAT A0_9 SOT8 AN1 AL1 OCU...

Page 201: ...D 15 DSP1_DAT A1_2 SCK11 DSP1_CT RL2 DSP0_CT RL2 OCU11_OTD 1 PPG11_TO UT2 MFS8_CS 1 PPC_PCF GR516 0x0160 P5_16 GPIO_POD R5 POD 16 DSP1_DAT A0_2 DSP1_CL K DSP0_CT RL3 OCU0_OTD0 PPG0_TO UT0 MFS8_CS 2 PP...

Page 202: ...0 OCU11_OTD 0 PPG11_TO UT0 PPC_PCF GR531 0x017E P5_31 GPIO_POD R5 POD 31 DSP0_DAT A0_2 DSP0_DA TA_D2 SCK0 TOT2 OCU11_OTD 1 PPG11_TO UT2 SCL0 PPC_PCF GR600 0x0180 P6_00 GPIO_POD R6 POD 0 DSP0_DAT A1_2...

Page 203: ...13 0x019A P6_13 GPIO_POD R6 POD 13 TRACE10 PPC_PCF GR614 0x019C P6_14 GPIO_POD R6 POD 14 TRACE11 PPC_PCF GR615 0x019E P6_15 GPIO_POD R6 POD 15 TRACE12 PPC_PCF GR616 0x01A0 P6_16 GPIO_POD R6 POD 16 TRA...

Page 204: ...hibited If setting the port will be operated as input independent on the register value of the GPIO_DDR The register for P2_19 for POF exists though the port only supports input not supports output Th...

Page 205: ...CLK DSP0_DATA_D DSP0_CLK DSP0_DATA_D DSP0_CLK GFXCORE_RSDS_INACTIVE P0_00 P0_01 P0_02 P0_03 P0_04 P0_05 P0_06 P0_07 P0_08 P0_09 P0_10 P0_11 P0_12 P0_13 P0_14 P0_15 P0_16 P0_17 P0_18 P0_19 P5_27 P5_28...

Page 206: ...register of target port makes input control to set to 0 The PPC_PCFGR PDE PUE register of target port makes disable Pull Up Pull Down to set to 0 Note Regarding the analog switch setting see CHAPTER o...

Page 207: ...TTL 77 75 P0_31 CMOS s TTL 78 76 P1_01 CMOS s TTL 79 77 P1_00 CMOS s TTL 80 78 P1_03 CMOS s TTL 81 79 P1_02 CMOS s TTL 84 82 P0_26 CMOS s MediaLB 85 83 P0_27 CMOS s MediaLB 86 84 P0_28 CMOS s MediaLB...

Page 208: ...153 147 P4_05 CMOS s Automotive 154 148 P4_06 CMOS s Automotive 155 149 P4_07 CMOS s Automotive 156 150 P4_08 CMOS s Automotive 157 151 P4_09 CMOS s Automotive 158 152 P4_10 CMOS s Automotive 159 153...

Page 209: ...omotive TTL 204 196 P5_13 CMOS s Automotive TTL 205 197 P5_14 CMOS s Automotive TTL 206 198 P5_15 CMOS s Automotive TTL 207 199 P5_16 CMOS s Automotive TTL 208 200 P5_17 CMOS s Automotive TTL 209 201...

Page 210: ...20mA 1 44 P0_02 2mA 5mA 10mA 20mA 1 45 P0_03 2mA 5mA 10mA 20mA 1 46 44 P0_04 2mA 5mA 10mA 20mA 1 47 45 P0_05 2mA 5mA 10mA 20mA 1 48 46 P0_06 2mA 5mA 10mA 20mA 1 49 47 P0_07 2mA 5mA 10mA 20mA 1 50 48 P...

Page 211: ...A 2mA 5mA 105 101 P3_05 1mA 2mA 5mA 106 102 P3_06 1mA 2mA 5mA 122 118 P3_18 1mA 2mA 5mA 123 P3_19 1mA 2mA 5mA 124 P3_20 1mA 2mA 5mA 133 127 P3_21 1mA 2mA 5mA 30mA 134 128 P3_22 1mA 2mA 5mA 30mA 135 12...

Page 212: ...175 P4_30 1mA 2mA 5mA 5mA 184 176 P4_31 1mA 2mA 5mA 5mA 185 177 P5_00 1mA 2mA 5mA 5mA 186 178 P5_01 1mA 2mA 5mA 5mA 187 179 P5_02 1mA 2mA 5mA 5mA 188 180 P5_03 1mA 2mA 5mA 5mA 189 181 P5_04 1mA 2mA 5...

Page 213: ...CFGR ODR 0 0 the drive capacity will be 2mA If PPC_PCFGR POF 2 0 2 the RSDS function setting and PPC_PCFGR ODR 0 1 the drive capacity will be 4mA 2 1 If the PPC_PCFGR POF 2 0 is configured as SDA or S...

Page 214: ...ECFGR PSSPADCTRL 0 3 6 2 Port Status Hold during PSS Mode All of the GPIO except ports in VCC3 area can be kept the port status during PSS mode by System Special Setting Register SYSC0_SPECFGR The bit...

Page 215: ...which is defined in the following table in order to satisfy AC specification Do not take a port combination which is not described in the following table as a port group Table 3 2 Function Port Group...

Page 216: ...1 P3_17 MFS8_CS2 P3_15 MFS8_CS3 Group2 P5_03 SCK8 P5_02 SOT8 P5_04 SIN8 P5_10 MFS8_CS0 P5_15 MFS8_CS1 P5_16 MFS8_CS2 P5_14 MFS8_CS3 Multi Function Serial Ch 9 Group1 P3_08 SCK9 P3_07 SOT9 P3_09 SIN9 P...

Page 217: ...Serial Ch 11 Group1 P3_16 SCK11 P3_15 SOT11 P3_17 SIN11 Group2 P5_15 SCK11 P5_14 SOT11 P5_16 SIN11 Group3 P4_27 SCK11 P4_26 SOT11 P4_28 SIN11 CAN Ch 1 Group1 P3_06 TX1 P3_05 RX1 Group2 P4_12 TX1 P4_1...

Page 218: ...i GPIO Key Code Register GPIO_KEYCDR Data Direction Clear Register GPIO_DDCRi GPIO Key Code Register GPIO_KEYCDR Port Output Data Register GPIO_PODRi Port Output Set Register GPIO_POSRi Port Output Cl...

Page 219: ...nfiguration procedure of resource I O port is described Category I O Direction Referable Procedure Remark Resource I O Port Both Direction See 5 1 Input See 5 2 Output See 5 3 Port Function Input See...

Page 220: ...s The dedicated input output direction configuration should be necessary for SCK MSF Start Disable analog input in case with analog function Configure a port input at RIC_RESINn PORTSEL 3 0 Configure...

Page 221: ...sable analog input in case with analog function Configure a port input at RIC_RESINn PORTSEL 3 0 Configure a resource input at RIC_RESINn RESSEL 3 0 Enable an input at PPC_PCFGRn PIE 1 Configure a res...

Page 222: ...bove A resource which supports neither relocation nor the other resource input doesn t have its RIC_RESINn register Configurations can be skipped in above procedure 5 3 Resource Output Figure 5 3 Proc...

Page 223: ...n Input Figure 5 4 Procedure of Port Input Start Disable analog input in case with analog function End Release input cut off function at GPIO_PORTEN GPORTEN 1 Configure the data direction to input at...

Page 224: ...t Number 002 04852 Rev G 223 5 5 Port Function Output Figure 5 5 Procedure of Port Output Start Disable analog input in case with analog function End Configure a resource output signal as GPIO at PPC_...

Page 225: ...ports have multiplexed usage Regarding the analog switch setting see CHAPTER of 12 10 8 BIT Analog to Digital Converter and CHAPTER of LCDC Controller D A Converter and FPD Link has dedicated Output P...

Page 226: ...ed noise filter for resource input See the following configuration for effective usage Table 6 1 Configuration for noise filter Resource PPC_PCFGRiij NFE EICxx_NFER NFE RLTn_TMCSR NFE RIC_RESINn RESSE...

Page 227: ...x resource channel number External pins GPIO for using some resources except EINTx TINx SCLx SDAx External pins GPIO for using ENINTx or TINx External pins GPIO for using SCLx SDAx of I2C NF for GPIO...

Page 228: ...cument Number 002 04852 Rev G 227 CHAPTER 12 State Transition This chapter explains the state transition 1 Overview 2 Diagram of State Transition 3 Fetching the Operation Mode 4 Changes to PSS and RUN...

Page 229: ...n 228 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1 Overview This section gives a brief overview of State transition Refer to the low power chapter for the detailed information for...

Page 230: ...es Hardware Manual Document Number 002 04852 Rev G 229 2 Diagram of State Transition This section shows diagram of state transitions The device state transitions for this series are shown below Figure...

Page 231: ...omain RUN Normal Operation RUN CPU Sleep PSS Timer mode PSS STOP mode PSS Timer mode shutdown PD6_ON PSS Timer mode shutdown PD6_OFF PSS STOP mode Shutdown CPU PD2 enable disable disable disable Power...

Page 232: ...TX CY MCU 1 or 2 4 DVCC LVDH1 reset or RSTX CY MCU or User 1 5 AVCC5 LVDH1 reset or RSTX CY MCU or User 1 6 VCC3 RSTX User 2 7 AVCC3 RSTX User 2 8 VCC12 Internal power controller reset User 6 9 AVCC3_...

Page 233: ...ponse L Regulator of flash memory Reset RESET SYSC SYStem Controller0 Reset RESET SYSC SYStem Controller0 Clock CPU operating Internal Power Domain state ON Internal Power Domain Reset H Regulator of...

Page 234: ...r release wait Regulator of flash stabilization wait skip Mode evaluation and Security evaluation and Internal reset release Fast CR 8cycle BootROM program operating User program operating Hard Reset...

Page 235: ...Factor release wait Regulator of flash stabilization wait skip Mode evaluation and Security evaluation and Internal reset release BootROM program operating User program operating Soft Reset Reset Fac...

Page 236: ...Controller0 1 Clock CPU operating Internal Power Domain state ON OFF Internal Power Domain Reset H L PSC1 1 ON OFF VCC12 1 ON OFF Flash memory state Standby Deep Sleep Backup RAM state Standby Sleep...

Page 237: ...esponse Regulator of flash memory Reset RESET SYSC SYStem Controller0 1 Reset H SYSC SYStem Controller0 1 Clock CPU operating Internal Power Domain state ON OFF Internal Power Domain Reset H L Flash m...

Page 238: ...1920cycle PSS RUN Updating RUN Profile processing description PSS power supply to All circuit From PSS mode to RUN change state Return from a power supply shutoff state WAKEUP Factor Internal Reset L...

Page 239: ...ument Number 002 04852 Rev G CHAPTER 13 Low voltage Detection This chapter explains the function of low voltage detection 1 Overview 2 Configuration and Block Diagram 3 Operation 4 Registers 5 Electri...

Page 240: ...supervision 2 Configuration and Block Diagram The block diagram shows LVDs hardware and software configuration Figure 2 1 LVD Hardware and Software Configuration LVDL0 LVDH0 LVDL1 LVDH1 LVDL2 LVDH2 E...

Page 241: ...ble PD2 power supply supervision LVDH2 VCC3 Configurable Reset or interrupt Configurable 3V I O power supply supervision Notes PONR will be generated by means of either LVDL0 or LVDH0 detected release...

Page 242: ...Not supported No 01 Not supported 10 0 97 Initial value 11 1 07 Note This LVD cannot be used to reliably generate a reset before voltage dips below minimum guaranteed MCU operation voltage bit24 LVDL1...

Page 243: ...moreover set EXVRSTCNT bit to 0 for other product than revsion M bit12 9 LVDH1V LVDH1 voltage setting bits Bits Detection Voltage V Guaranteed MCU operation range 0000 2 35 No 1 0001 2 75 0010 2 85 0...

Page 244: ...alue No 1 0001 2 75 0010 2 85 Yes 0011 Not supported 0100 Not supported 0101 Not supported 0110 Not supported 0111 Not supported 1000 Not supported 1001 Not supported 1010 Not supported 1011 Not suppo...

Page 245: ...CHAPTER 13 Low voltage Detection 244 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 5 Electric Characteristics See the datasheet...

Page 246: ...l Document Number 002 04852 Rev G 245 CHAPTER 14 Serial Programming This chapter explains serial programming 1 Overview 2 Memory Map 3 FLASH Sector Configuration 4 Port Configuration 5 Operation 6 Not...

Page 247: ...SH of Traveo Platform hardware manual 4 Port Configuration Table 4 1 Port Configuration and Usage Port Name Configuration Remark MODE Pull down RSTX Reset input X0 Oscillation input X1 Oscillation out...

Page 248: ...load start address A31 A24 6 XXH Download count number BC7 BC0 7 XXH Download count number BC15 BC8 8 XXH Download count number BC23 BC16 9 XXH Download count number BC31 BC24 10 XXH Sum value of down...

Page 249: ...ta For adjusting of command length 6 00H Dummy data For adjusting of command length 7 00H Dummy data For adjusting of command length 8 00H Dummy data For adjusting of command length 9 00H Dummy data F...

Page 250: ...e of download data 1 1 Byte Download processing response Busy Normal end SUM malfunction 00H 01H 02H 1 About downloaded N byte data SUM value is calculated in 8 bits and the overflow of simple additio...

Page 251: ...response 1 Normal end 11H 1 Response of reset command is always normal end 11H Full Chip Erase Command Sequence Byte Count Host Tool Micom Micom Host Tool 1 32 Byte Key0 7Receive 4 Byte Command respon...

Page 252: ...lue error response Download command SUM value error Reception of download data SUM value error response SUM value error SUM value error response Download process response Command error response Yes Ye...

Page 253: ...power supply devises will output low during external reset low is inputted to RSTX in SERIAL PROGRAMMING MODE After reset high is inputted to RSTX PSC port will output high If 1 2V power supply is sup...

Page 254: ...CHAPTER 15 12 10 8 bit Analog to Digital Converter This chapter explains the functions and operations of the 12 10 8 bit A D Converter 1 Overview 2 Configuration and Block Diagram 3 Operation of A D...

Page 255: ...ot be interrupted hence the wait time between the higher priority conversion request and its conversion start can be up to the maximum A D conversion period In case of multiple conversion channel proc...

Page 256: ...go idle power down state it can start A D sampling without the resumption time Interrupt request generation to CPU is provided for Conversion done interrupt end of a logical channel conversion Group...

Page 257: ...nalog input selection Arbiter 64 12bit ADC Start ANIN Result Analog mux AN0 AN1 AN2 AN3 AN4 ANm Analog input pins Result register Logical channel Trigger and grouping logic HW trigger inputs one per l...

Page 258: ...D Pulse Detection function detects events of desired length and also filters parasitic inverted events Each logical channel has a dedicated pulse detection function 3 1 A D Conversion Flow The basic...

Page 259: ...gister ADC12Bn_CDi the conversion done interrupt flag is set and the trigger status is cleared 6 Started next conversion of the logical channel with the highest priority at the moment If there is no t...

Page 260: ...me If a conversion is finished and the data of the previous conversion of the same channel has not been read out previous data could be overwritten and previous conversion result lost To avoid this th...

Page 261: ...ST 01 when setting DP to 1 disable the group interrupted interrupt set the corresponding ADC12Bn_GRPIRQE0 GRPIRQE0 to 3 to 0 The conversion result will be protected only after all conversions of the m...

Page 262: ...ion completion It does not make sense to configure the first logical channel to trigger type 2 since the channels would never be triggered Idle trigger TRGTYP 11 the trigger status flags are set whene...

Page 263: ...s number is higher 3 Logical channel 60 Although the channel 59 has higher priority its trigger status is not set and even the data protection is active Moreover logical channel 6 has the same priorit...

Page 264: ...he group 2 would be converted first due to higher priority setting Since the first channel in the groups has the highest priority the groups are re triggerable if the next starting channel trigger app...

Page 265: ...ority conversion requests are executed Note that RSMRST setting of the first channel in the group does not matter since the group cannot be interrupted before the conversion of its first channel start...

Page 266: ...gger is issued and processing of the group 0 is initiated 2 Processing of the group 0 conversion of logical channels 0 1 2 start of channel 3 conversion 3 Logic channel 6 trigger is issued during the...

Page 267: ...Figure 3 7 Resuming of the Group Processing Forced Stop Mode is Disabled ADC12Bn_CTRL FSMD 0 Restart group setting RSMRST 1 0 10 for a logical channel configures that if the group is interrupted just...

Page 268: ...of the channel 3 the processing of the group 0 is interrupted during the conversion of channel 3 and trigger status of channel 0 is set Forced stop mode is disabled ADC12Bn_CTRL FSMD 0 Since the prio...

Page 269: ...of forced stop mode ADC12Bn_CTRL FSMD Forced stop mode is enabled ADC12Bn_CTRL FSMD 1 Figure 3 9 4 Since the priority of the channel 6 is higher than priority of the channel 5 the processing of the gr...

Page 270: ...d channel set to resume These way subgroups can be formed within a group 1 Logic channel 0 trigger is issued and processing of the group 0 is initiated 2 Processing of the group 0 conversion of logica...

Page 271: ...gher than priority of the channel 4 the processing of the group 0 is interrupted after the conversion of channel 3 is finished and trigger status of channel 1 is set channel 1 is the last converted ch...

Page 272: ...ith higher priority is issued during multiple conversion the multiple conversion channel is interrupted after interrupt operation and the conversion of the channel with the higher priority is started...

Page 273: ...rsion counter It is cleared by next conversion request 01 Resume Keeps the trigger status flag set and current value of the conversion counter 10 Restart The trigger status flag stays set only if the...

Page 274: ...bgroup is set The conversion counter is cleared immediately It means that the accumulated conversion result before the interrupt is not really usable because it is not known how many conversions are d...

Page 275: ...version cannot stop Writing ADC12Bn_CTRL FSTP 1 invalid Writing 1 to the corresponding bits of ADC12Bn_TRGCL1 to 0 TRGCL or ADC12Bn_CHCTRLi TRGCL The corresponding trigger status flag is reset immedia...

Page 276: ...racteristics of A D Converter would have transition between digital values 0x000 and 0x001 at AVRL 0 5LSB input voltage level and transition between digital values 0xFFEh and 0xFFF at AVRH 1 5LSB inpu...

Page 277: ...ferent ADC12Bn_GCV GCV settings trigger the multiple conversion channel i e perform AVRL voltage conversion It is better to configure multiple conversions of AVRL and calculate average result Find ADC...

Page 278: ...verted operation i e ADC12Bn_CHCTRL0 to 63 RCINVSEL 1 Over threshold flags ADC12Bn_RCOTF0 to 1 RCOTF and ADC12Bn_CHSTAT0 to 63 RCOTF showing that the A D conversion value exceeded the upper threshold...

Page 279: ...DC12Bn_RCOL2 ADC12Bn_RCOL1 ADC12Bn_RCOL0 8 bit range comparator ADC12Bn_CHCTRL0 63 FRCMD 0 MUX MUX RCSEL 2 0 RCINVSEL RCEN Over Threshold Flags Interrupt flags Interrupt Comparator result Pulse detect...

Page 280: ...COH0 ADC12Bn_FRCOL7 ADC12Bn_FRCOL6 ADC12Bn_FRCOL5 ADC12Bn_FRCOL4 ADC12Bn_FRCOL3 ADC12Bn_FRCOL2 ADC12Bn_FRCOL1 ADC12Bn_FRCOL0 Resolution of A D conversion ADC12Bn_CTRL Range Comparator Control ADC12Bn_...

Page 281: ...TRL0 to 63 PCTNCT decrements with each negative event The purpose of the positive counter is to detect consecutive range comparator events of desired length The negative counter can be used to force a...

Page 282: ...12Bn_PCIRQC0 PCIRQC0 b Positive counter decrements with positive events c Positive counter expires becomes equal to 0 the pulse counter interrupt flag PCIRQ is set d A series of negative events does n...

Page 283: ...version continues with the next channel from where it had stopped For the definition of debug state refer to Section 12 8 of the Arm Cortex R5 Technical Reference Manual The ADC12Bn_STAT BUSY flag is...

Page 284: ...cedure of A D converter 4 1 Control of A D Conversion Figure 4 1 shows main flow of controlling A D converter Figure 4 1 Main Flow of Controlling A D Converter Start of A D conversion control Setting...

Page 285: ...ing ADC12Bn_ST0 3 Gain compensation setting ADC12Bn_GCV Offset compensation setting ADC12Bn_OCV Resolution setting ADC12Bn_CTRL RES 1 0 Debug enable setting ADC12Bn_CTRL DBGE ACH register mode setting...

Page 286: ...ADC12Bn_CHCTRL0 63 RSMRST 1 0 Data protection enable setting ADC12Bn_CHCTRL0 63 DP Sampling time select setting ADC12Bn_CHCTRL0 63 SMTIME 1 0 A D conversion done interrupt enable setting ADC12Bn_CDONE...

Page 287: ...ange comparator disable ADC12Bn_CHCTRL0 63 RCEN 0 Set as range comparator enable ADC12Bn_CHCTRL0 63 RCEN 1 Select 12 bit 8 bit range comparator mode 12 bit mode 8 bit mode Set as 12 bit range comparat...

Page 288: ...tection Start setting of pulse detection Uses a pulse detection Yes No End setting of pulse detection Positive counter reload value setting ADC12Bn_PCCTRL0 63 PCTPRL 7 0 Negative counter reload value...

Page 289: ...GTYP 1 0 10 idle trigger TRGTYP 1 0 11 Detect conversion done interrupt Yes No Read conversion done interrupt flag of channel i ADC12Bn_CDONEIRQ0 1 CDONEIRQ Read conversion data of channel i ADC12Bn C...

Page 290: ...ersion of group 0 is not interrupted and finished A D conversion request trigger of the first channel of group 0 Read conversion data of group 0 ADC12Bn CD0 63 Group interruption End of group conversi...

Page 291: ...e comparator interrupt flag of channel i ADC12Bn_RCIRQ0 1 RCIRQ Checks for inside range or outside range of channel i ADC12Bn_CHCTRLi RCINVSEL Checks for inside range RCINVSEL 1 Checks for outside ran...

Page 292: ...i Start of pulse detection channel i Detect pulse detection interrupt Yes No Read pulse detection interrupt flag of channel i ADC12Bn_PCIRQ0 1 PCIRQ Clear pulse detection interrupt flag of channel i...

Page 293: ...DC12Bn_RCIRQE0 to 1 Range Comparator Interrupt Clear Registers ADC12Bn_RCIRQC0 to 1 Pulse Counter Interrupt Flags ADC12Bn_PCIRQ0 to 1 Pulse Counter Interrupt Enable Registers ADC12Bn_PCIRQE0 to 1 Puls...

Page 294: ...0 BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME Reserved TRGCL SWTRG ACCESS_TYPE R0 W0 R0 W R0 W PROT_TYPE INITIAL_VALUE 0x00 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME RCEN RCINVSEL Reserved RCSEL...

Page 295: ...Enable bit Bit Description 0 Range comparator disabled 1 Range comparator enabled bit22 RCINVSEL Range Comparator Inverted Range Selection bit Bit Description 0 The comparison checks for outside range...

Page 296: ...rsion of this channel is started resume the group processing with this channel 10 Restart After the group is interrupted restart with the start channel or the last converted channel configured as resu...

Page 297: ...g to Digital Converter 296 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G bit5 0 ANIN 5 0 Analog Input Selection bits ANIN 5 0 Description 000000 Analog input AN0 is selected 111111 An...

Page 298: ...PE OTHER A D Channel Status Register ADC12Bn_CHSTAT0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE RX WX PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME Reserved RCOT...

Page 299: ...o 1 register description bit2 GRPIRQ Group Interrupted Interrupt flag Bit Description 0 Not detected 1 Group interrupted interrupt detected This bit is identical to the corresponding bit in the ADC12B...

Page 300: ...AME D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 ACCESS_TYPE R WX R WX R WX R WX R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE X X X X X X X X bit15 0 D 15 0 A D Conversion Data bits These bits store the conversion...

Page 301: ...3 D 2 D 1 D 0 ACCESS_TYPE R WX R WX R WX R WX R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE X X X X X X X X bit15 12 Reserved Reserved bits Reading this bit returns an undefined Writing data to these bi...

Page 302: ...3 NUMERIC_TYPE OTHER Pulse Counter Control Register ADC12Bn_PCCTRL0 BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME Reserved PCTNCT 4 PCTNCT 3 PCTNCT 2 PCTNCT 1 PCTNCT 0 ACCESS_TYPE RX WX R WX R WX R WX R...

Page 303: ...e event from the appropriate range comparator For further explanation of negative events and operation of pulse detection function refer to section Pulse Detection Function in chapter 3 Operation of A...

Page 304: ...CDONEIRQ2 7 CDONEIRQ2 6 CDONEIRQ2 5 CDONEIRQ2 4 ACCESS_TYPE R WX R WX R WX R WX R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME CDONEIRQ2 3 CDO...

Page 305: ...GST bits is still 1 In case of multiple conversion channels this bit is set when the last conversion is done final conversion result is accumulated and corresponding trigger status ADC12Bn_TRGST0 TRGS...

Page 306: ...IAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME CDONEIRQ3 9 CDONEIRQ3 8 CDONEIRQ3 7 CDONEIRQ3 6 CDONEIRQ3 5 CDONEIRQ3 4 CDONEIRQ3 3 CDONEIRQ3 2 ACCESS_TYPE R WX R WX R WX R WX R WX R WX...

Page 307: ...27 CDONEIRQ E26 CDONEIRQ E25 CDONEIRQ E24 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME CDONEIRQ E23 CDONEIRQ E22 CDON...

Page 308: ...1 0 CDONEIRQE31 to 0 Conversion Done Interrupt Enable bits Bit Description 0 Conversion done interrupt disabled 1 Conversion done interrupt enabled Conversion done interrupt is issued when the bit is...

Page 309: ...TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME CDONEIRQ E47 CDONEIRQ E46 CDONEIRQ E45 CDONEIRQ E44 CDONEIRQ E43 CDONEIRQ E42 CDONEIRQ E41 CDONEIRQ E40 ACCESS_TYPE R W R W...

Page 310: ...CDONEIRQ C27 CDONEIRQ C26 CDONEIRQ C25 CDONEIRQ C24 ACCESS_TYPE R0 W R0 W R0 W R0 W R0 W R0 W R0 W R0 W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME CDONEIRQ C23...

Page 311: ...02 04852 Rev G bit31 0 CDONEIRQC31 to 0 Conversion Done Interrupt Clear bits Bit Description 0 No effect 1 Conversion Done Interrupt cleared When this bit is set to 1 the corresponding bit in the ADC1...

Page 312: ...0 W R0 W R0 W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME CDONEIRQ C47 CDONEIRQ C46 CDONEIRQ C45 CDONEIRQ C44 CDONEIRQ C43 CDONEIRQ C42 CDONEIRQ C41 CDONEIRQ C40...

Page 313: ...PIRQ20 GRPIRQ19 GRPIRQ18 GRPIRQ17 GRPIRQ16 ACCESS_TYPE R WX R WX R WX R WX R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME GRPIRQ15 GRPIRQ14 GRPIR...

Page 314: ...id not win arbitration for the next conversion i e there was a channel with active trigger status and higher priority For multiple conversion logical channels this bit is set to 1 also in the case the...

Page 315: ...S_TYPE R WX R WX R WX R WX R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 bit31 0 GRPIRQ63 to 32 Group Interrupted Interrupt flags for the case the group gets interrupted and stopped befo...

Page 316: ...1 20 19 18 17 16 BIT_NAME GRPIRQE23 GRPIRQE22 GRPIRQE21 GRPIRQE20 GRPIRQE19 GRPIRQE18 GRPIRQE17 GRPIRQE16 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET...

Page 317: ...PE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME GRPIRQE47 GRPIRQE46 GRPIRQE45 GRPIRQE44 GRPIRQE43 GRPIRQE42 GRPIRQE41 GRPIRQE40 ACCESS_TYPE R W R W R W R W R W R W R W R W P...

Page 318: ...IAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME GRPIRQC23 GRPIRQC22 GRPIRQC21 GRPIRQC20 GRPIRQC19 GRPIRQC18 GRPIRQC17 GRPIRQC16 ACCESS_TYPE R0 W R0 W R0 W R0 W R0 W R0 W R0 W R0...

Page 319: ...W R0 W R0 W R0 W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME GRPIRQC47 GRPIRQC46 GRPIRQC45 GRPIRQC44 GRPIRQC43 GRPIRQC42 GRPIRQC41 GRPIRQC40 ACCESS_TYPE R0 W R0...

Page 320: ...TIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME RCIRQ23 RCIRQ22 RCIRQ21 RCIRQ20 RCIRQ19 RCIRQ18 RCIRQ17 RCIRQ16 ACCESS_TYPE R WX R WX R WX R WX R WX R WX R WX R WX PROT_TYPE INI...

Page 321: ...itions The range comparison for this channel is enabled ADC12B_CHCTRL0 to 31 RCEN is set The conversion of the logical channel is just finished An interrupt condition is met see Table 5 1 This bit is...

Page 322: ...R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME RCIRQ39 RCIRQ38 RCIRQ37 RCIRQ36 RCIRQ35 RCIRQ34 RCIRQ33 RCIRQ32 ACCESS_TYPE R WX R WX R WX R WX R WX R W...

Page 323: ...12Bn_CHCTRL0 to 63 RCINVSEL Conversion Result above Upper Threshold Conversion Result below Lower Threshold Interrupt Condition outside range 0 1 x INT condition above range ADC12Bn_RCOTF0 to 1 RCOTF...

Page 324: ...ET 23 22 21 20 19 18 17 16 BIT_NAME RCIRQE23 RCIRQE22 RCIRQE21 RCIRQE20 RCIRQE19 RCIRQE18 RCIRQE17 RCIRQE16 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFS...

Page 325: ..._TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME RCIRQE47 RCIRQE46 RCIRQE45 RCIRQE44 RCIRQE43 RCIRQE42 RCIRQE41 RCIRQE40 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_T...

Page 326: ...ITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME RCIRQC23 RCIRQC22 RCIRQC21 RCIRQC20 RCIRQC19 RCIRQC18 RCIRQC17 RCIRQC16 ACCESS_TYPE R0 W R0 W R0 W R0 W R0 W R0 W R0 W R0 W PROT...

Page 327: ...R0 W R0 W R0 W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME RCIRQC47 RCIRQC46 RCIRQC45 RCIRQC44 RCIRQC43 RCIRQC42 RCIRQC41 RCIRQC40 ACCESS_TYPE R0 W R0 W R0 W R0 W...

Page 328: ...23 22 21 20 19 18 17 16 BIT_NAME PCIRQ23 PCIRQ22 PCIRQ21 PCIRQ20 PCIRQ19 PCIRQ18 PCIRQ17 PCIRQ16 ACCESS_TYPE R WX R WX R WX R WX R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET...

Page 329: ...ev G positive counter and negative counter are stopped as long as the pulse counter interrupt flag of the appropriate channel is set This bit is cleared by writing 1 to the corresponding bit in the AD...

Page 330: ...R WX R WX R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME PCIRQ39 PCIRQ38 PCIRQ37 PCIRQ36 PCIRQ35 PCIRQ34 PCIRQ33 PCIRQ32 ACCESS_TYPE R WX R WX R WX R W...

Page 331: ...T 23 22 21 20 19 18 17 16 BIT_NAME PCIRQE23 PCIRQE22 PCIRQE21 PCIRQE20 PCIRQE19 PCIRQE18 PCIRQE17 PCIRQE16 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSE...

Page 332: ...OT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME PCIRQE47 PCIRQE46 PCIRQE45 PCIRQE44 PCIRQE43 PCIRQE42 PCIRQE41 PCIRQE40 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT...

Page 333: ...L_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME PCIRQC23 PCIRQC22 PCIRQC21 PCIRQC20 PCIRQC19 PCIRQC18 PCIRQC17 PCIRQC16 ACCESS_TYPE R0 W R0 W R0 W R0 W R0 W R0 W R0 W R0 W PROT_TYP...

Page 334: ...ual Document Number 002 04852 Rev G 333 Additionally the corresponding positive and negative counter ADC12Bn_PCCTRL0 to 31 PCTPCT and ADC12Bn_PCCTRL0 to 31 PCTNCT are reloaded with their reload values...

Page 335: ...5 PCIRQC44 PCIRQC43 PCIRQC42 PCIRQC41 PCIRQC40 ACCESS_TYPE R0 W R0 W R0 W R0 W R0 W R0 W R0 W R0 W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME PCIRQC39 PCIRQC38 PCIRQC3...

Page 336: ...CCESS_TYPE R WX R WX R WX R WX R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME TRGST23 TRGST22 TRGST21 TRGST20 TRGST19 TRGST18 TRGST17 TRGST16 A...

Page 337: ...to 63 RSMRST 01 This bit is cleared under one of the following conditions Completion of the logical channel conversion the last conversion in the case of multiple conversion channels at the same time...

Page 338: ...R WX R WX R WX R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 bit31 0 TRGST63 to 32 A D Channel Trigger Status flags Bit Description 0 No conversion request 1 Conversion request is issued...

Page 339: ...G Writing 1 to the corresponding bit in the ADC12Bn_TRGCL1 register or writing 1 to the corresponding ADC12Bn_CHCTRL32 to 63 TRGCL bit When setting and clearing of the bit takes place at the same tim...

Page 340: ...E INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME TRGCL23 TRGCL22 TRGCL21 TRGCL20 TRGCL19 TRGCL18 TRGCL17 TRGCL16 ACCESS_TYPE R0 W R0 W R0 W R0 W R0 W R0 W R0 W R0 W PROT_TYP...

Page 341: ...abled ADC12Bn_CTRL FSMD 0 A D conversion is not stopped but A D conversion result is not updated Hence when the next conversion is already requested the wait time from trigger status flag clear to the...

Page 342: ...TRGCL36 TRGCL35 TRGCL34 TRGCL33 TRGCL32 ACCESS_TYPE R0 W R0 W R0 W R0 W R0 W R0 W R0 W R0 W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 bit31 0 TRGCL63 to 32 Trigger Status Clear bits Bit Description 0 No...

Page 343: ...es Hardware Manual Document Number 002 04852 Rev G Note If forced stop is disabled ADC12Bn_CTRL FSMD 0 do not set trigger status flag again during the same conversion after the trigger status is clear...

Page 344: ...0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME TRGOR23 TRGOR22 TRGOR21 TRGOR20 TRGOR19 TRGOR18 TRGOR17 TRGOR16 ACCESS_TYPE R WX R WX R WX R WX R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0...

Page 345: ...s Hardware Manual Document Number 002 04852 Rev G Software and hardware trigger are issued at the same cycle and corresponding trigger type ADC12Bn_CHCTRL0 to 31 TRGTYP 1 0 is set to 01 Writing 1 to t...

Page 346: ...R43 TRGOR42 TRGOR41 TRGOR40 ACCESS_TYPE R WX R WX R WX R WX R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME TRGOR39 TRGOR38 TRGOR37 TRGOR36 TRGOR35 TRGO...

Page 347: ...R0 W R0 W R0 W R0 W R0 W R0 W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME TRGORC23 TRGORC22 TRGORC21 TRGORC20 TRGORC19 TRGORC18 TRGORC17 TRGORC16 ACCESS_TYPE R0...

Page 348: ...C48 ACCESS_TYPE R0 W R0 W R0 W R0 W R0 W R0 W R0 W R0 W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME TRGORC47 TRGORC46 TRGORC45 TRGORC44 TRGORC43 TRGORC42 TRGORC41...

Page 349: ...0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME RCOTF23 RCOTF22 RCOTF21 RCOTF20 RCOTF19 RCOTF18 RCOTF17 RCOTF16 ACCESS_TYPE R WX R WX R WX R WX R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0...

Page 350: ...nversion result is less than or equal to the upper threshold 1 The conversion result is above the upper threshold This bit is updated only in the case the corresponding interrupt flag ADC12Bn_RCIRQ0 R...

Page 351: ...TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME RCOTF39 RCOTF38 RCOTF37 RCOTF36 RCOTF35 RCOTF34 RCOTF33 RCOTF32 ACCESS_TYPE R WX R WX R WX R WX R WX R WX R WX R WX PROT_TYPE INI...

Page 352: ...3 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 W0 PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME Reserved CDCHEN CDCHNUM 5 CDCHNUM 4 CDCHNUM 3 CDCHNUM 2 CDCHNUM 1 CDCHNUM 0 ACCESS_T...

Page 353: ...annel selected for conversion done interrupt for triggering a DMA request CDCHNUM 5 0 Description 000000 Logical channel 0 selected 000001 Logical channel 1 selected 111111 Logical channel 63 selected...

Page 354: ...g Register ADC12Bn_CT BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME CT 15 CT 14 CT 13 CT 12 CT 11 CT 10 CT 9 CT 8 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OF...

Page 355: ...er ADC12Bn_RT BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 W0 PROT_TYPE INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME RT 7 RT 6 RT 5 RT 4 RT 3 RT 2 RT 1 RT 0 ACCESS_TYPE...

Page 356: ...IC_TYPE OTHER A D Converter Sampling Time Setting Register ADC12Bn_ST0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME ST 15 ST 14 ST 13 ST 12 ST 11 ST 10 ST 9 ST 8 ACCESS_TYPE R W R W R W R W R W R W R W R...

Page 357: ...INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME OCV 7 OCV 6 OCV 5 OCV 4 OCV 3 OCV 2 OCV 1 OCV 0 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 1 0 bit15 8 Rese...

Page 358: ..._TYPE INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME Reserved GCV 4 GCV 3 GCV 2 GCV 1 GCV 0 ACCESS_TYPE R0 W0 R W R W R W R W R W PROT_TYPE INITIAL_VALUE 000 0 0 0 0 0 bit15 5 Reserved Reserve...

Page 359: ...and request full range comparator mode and power down disable mode REGISTER_NAME ADC12Bn_CTRL OFFSET 0x3A0 ACCESS_SIZE B H W MULTIPLE 1 NUMERIC_TYPE OTHER A D Converter Global Control Register ADC12Bn...

Page 360: ...ode FSMD 1 Bit Description Read Write 0 The value is always 0 No effect 1 Request forced stop of A D conversion When the not forced stop mode FSMD 0 0 is always read from this bit Writing 0 or 1 to th...

Page 361: ...verter completes the current conversion but further conversion is stopped When the processor leaves debug state or DBGE is set to 0 conversion continues with the next channel from where it had stopped...

Page 362: ...R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 bit15 7 Reserved Reserved bits Reading this bit returns an undefined Writing data to these bits has no effect on the operation bit6 BUSY A D...

Page 363: ...HCTRL0 to 63 TRGTYP 1 0 11 there will be always at least one conversion request active and after BUSY flag is set first time to 1 it will not change bit5 0 ACH 5 0 Converted logical channel number Thi...

Page 364: ...n_RCOH7 have similar bit fields REGISTER_NAME ADC12Bn_RCOHi i 0 to 7 OFFSET 0x03B1 i 2 ACCESS_SIZE B H W MULTIPLE 0 7 NUMERIC_TYPE OTHER Range Comparator Upper Threshold Register 0 ADC12Bn_RCOH0 BIT_O...

Page 365: ...RCOL7 have similar bit fields REGISTER_NAME ADC12Bn_RCOLi i 0 to 7 OFFSET 0x03B0 i 2 ACCESS_SIZE B H W MULTIPLE 0 7 NUMERIC_TYPE OTHER Range Comparator Lower Threshold Register 0 ADC12Bn_RCOL0 BIT_OFF...

Page 366: ...OTHER Full Range Comparator Upper Threshold Register 0 ADC12Bn_FRCOH0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved FRCOH 11 FRCOH 10 FRCOH 9 FRCOH 8 ACCESS_TYPE R0 W0 R W R W R W R W PROT_TYPE...

Page 367: ...bits of A D conversion result If 8 bit resolution ADC12Bn_CTRL RES 1 0 11 FRCOH 11 8 Not used for 8 bit range comparator FRCOH 7 0 Compares the 8 bits of A D conversion result Selection of one of eigh...

Page 368: ...OTHER Full Range Comparator Lower Threshold Register 0 ADC12Bn_FRCOL0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved FRCOL 11 FRCOL 10 FRCOL 9 FRCOL 8 ACCESS_TYPE R0 W0 R W R W R W R W PROT_TYPE...

Page 369: ...bits of A D conversion result If 8 bit resolution ADC12Bn_CTRL RES 1 0 11 FRCOL 11 8 Not used for 8 bit range comparator FRCOL 7 0 Compares the 8 bits of A D conversion result Selection of one of eigh...

Page 370: ..._OFFSET 7 6 5 4 3 2 1 0 BIT_NAME Reserved AVRHSEL AVRLSEL ICIRQY CNVNUM 3 CNVNUM 2 CNVNUM 1 CNVNUM 0 ACCESS_TYPE R0 W0 R W R W R W R W R W R W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 bit7 Reserved...

Page 371: ...s in case the conversion request with higher priority is issued Bit Description 0 Multiple conversion logical channel can be interrupted between single conversions 1 Multiple conversion logical channe...

Page 372: ...TYPE OTHER A D Multiple Conversion Channel Status Register ADC12Bn_MCSTAT0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME Reserved MCCNT 4 MCCNT 3 MCCNT 2 MCCNT 1 MCCNT 0 ACCESS_TYPE RX WX R WX R WX R WX R WX R...

Page 373: ...04852 Rev G CHAPTER 16 Stepper Motor Controller This chapter explains the functions and operations of the Stepper Motor Controller SMC 1 Overview 2 Configuration and Block Diagram 3 Operation of the...

Page 374: ...ontrolled by a combination of the PWM Pulse Generator and selector logic circuits Two PWM Pulse Generators with 10 bit 8 bit operation mode selected by software For the PWM pulse width in 8 bit operat...

Page 375: ...oller 374 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 2 Configuration and Block Diagram This section shows block diagrams of the Stepper Motor Controller Figure 2 1 Block Diagram of...

Page 376: ...Stepper Motor Controller pins PWM Control Register PWC The PWM Control Register PWC starts stops the Stepper Motor Controller sets the PWM Prescaler and selects the operation mode for the PWM Pulse G...

Page 377: ...that controls the PWM period When the Operation Mode Switching bit PWC SC is set to 0 8 bit operation mode is selected PWM period 256 counts If this bit is set to 1 10 bit operation mode is selected P...

Page 378: ...se Generator starts the counter that controls the PWM period The counter increments its value from 0x00 0x000 at the rising edge of the PWM operating clock The PWM Pulse Generator output remains at th...

Page 379: ...setting of the PWM pulse width duty cycle and the output pin selection settings are reflected on the Stepper Motor Controller outputs To avoid this scenario clear PWC CE only after PWS BS is automati...

Page 380: ...CHAPTER 16 Stepper Motor Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 379 Figure 3 2 Example of the Setting Procedure for the Stepper Motor Controller...

Page 381: ...pin is done by configuring the PWM Selection Register PWS P2 2 0 PWS M2 2 0 PWS P1 2 0 PWS M1 2 0 Table 3 2 Selection of Motor Drive Signals and Setting of PWM1 Selection Bits PWS P1 2 0 PWM1P PWS M1...

Page 382: ...e same software access is allowed When the Output Update bit PWS BS is set to 1 by software and the end of current PWM cycle is detected PWM Pulse Generator and motor drive selection logic will load v...

Page 383: ...epper Motor Controller starts operating The delay time is configured in the SMC Trigger Delay Register PTRGDL The Stepper Motor Controller will continue to operate until the Count Enable bit PWC CE is...

Page 384: ...CHAPTER 16 Stepper Motor Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 383 Figure 3 4 Flowchart for Triggering Stepper Motor Controller...

Page 385: ...r Controller Figure 3 5 shows how the trigger starts Stepper Motor Controller PTRGDL 0x01 If the SMC Trigger Delay Register PTRGDL setting is 0x00 PWC CE is set immediately after receiving the trigger...

Page 386: ...WM Control Register PWC PWM1 and PWM2 Compare Registers PWC1 PWC2 PWM Selection Register PWS PWM Selection Set Register PWSS SMC Trigger Delay Register PTRGDL Table 4 1 List of Registers for the Stepp...

Page 387: ...W R W R W R0 W0 R0 W0 PROT_TYPE Rp Wp INITIAL_VALUE 0 0 0 0 0 0 bit15 10 Reserved Reserved bits When writing always write 0 When reading 0 is always read bit9 P 3 PWM Operating Clock Prescaler bit P...

Page 388: ...r the PWM1 Pulse Generator is started The CE bit can be set and cleared by the software This bit also can be set to 1 by receiving trigger To receive trigger the CE bit must first be cleared to 0 Bit...

Page 389: ...n mode of the PWM Pulse Generators Bit Description 0 8 bit operation mode is selected 1 10 bit operation mode is selected Note The PWC CE bit shall be set to 1 after the setting of the PWM Operating C...

Page 390: ...10 9 8 BIT_NAME Reserved D 9 8 ACCESS_TYPE R0 W0 R W PROT_TYPE Rp Wp INITIAL_VALUE 0 X BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME D 7 0 ACCESS_TYPE R W PROT_TYPE Rp Wp INITIAL_VALUE X bit15 10 Reserved Rese...

Page 391: ...mode D 9 8 PWC2 D 9 8 bits are don t care The software must always make a 16 bit write access to PWM1 and PWM2 Compare Registers PWC1 PWC2 to ensure consistency of data However 8 bit write access to...

Page 392: ...le When the Operation Mode Switching bit is set to 8 bit operation mode PWC SC 0 the compare data value is taken from D 7 0 bits and D 9 8 bits are don t care When the Operation Mode Switching bit is...

Page 393: ...Series Hardware Manual Document Number 002 04852 Rev G If the PWS BS bit is 1 don t change the PWM Compare Register Compare Data Value PWC1 D 9 0 D 9 0 and the PWM Selection Register Output Selection...

Page 394: ...put Update bit BS synchronously updates the Selector Output Selection bits and PWM Pulse Generator Compare Data Value See Figure3 3 To change the settings for the PWM duty cycle or output pin states t...

Page 395: ...e PWM2P output 1XX Hi Z PWM2P output is set to high impedance X don t care Note If the PWS BS bit is 1 don t change the PWM Compare Register Compare Data Value PWC1 D 9 0 PWC2 D 9 0 and the PWM Select...

Page 396: ...PWC2 D 9 0 and the PWM Selection Register Output Selection bits PWS P2 2 0 PWS M2 2 0 P1 2 0 PWS M1 2 0 bit2 0 M1 2 0 Minus Output 1 Selection bits The M1 2 0 bits selects the output signal for PWM1M...

Page 397: ...When reading 0 is always read bit14 BSS Set bit for the Output Update bit This bit sets the value of PWS BS bit Bit Description 0 No effect 1 Sets the PWS BS bit to 1 Reading of this bit returns 0 Not...

Page 398: ...CHAPTER 16 Stepper Motor Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 397 bit13 0 Reserved Reserved bits When writing always write 0 When reading 0 is always read...

Page 399: ...E Rp Wp INITIAL_VALUE 0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME D 7 0 ACCESS_TYPE R W PROT_TYPE Rp Wp INITIAL_VALUE 0 bit15 8 Reserved Reserved bits When writing always write 0 When reading 0 is always re...

Page 400: ...02 04852 Rev G 399 CHAPTER 17 Trigger Configuration of Stepper Motor Controller This chapter explains the trigger configuration of stepper motor controller 1 Overview 2 Configuration and Block Diagram...

Page 401: ...the register name indicates that the register is an instance g of the SMC Trigger Generator The suffix i in the register name indicates that the register is an instance i of the SMC channel Figure 2 1...

Page 402: ...er Motor Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 401 3 Operation The trigger configuration and its operation is described in 4 4 Registers Offset Register Name 0x0000...

Page 403: ...S25 S24 S23 S22 S21 S20 ACCESS_TYPE R0 WX R W R W R W R W R W R W PROT_TYPE Rp Wp INITIAL_VALUE 0 0 0 0 0 0 0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME Reserved S15 S14 S13 S12 S11 S10 ACCESS_TYPE R0 WX R W...

Page 404: ...or the SMC trigger group S2 triggered by SMCTGg_PTRG TR2 Bit Description 0 SMC 6 g 1 is not triggered by SMCTGg_PTRG TR2 1 SMC 6 g 1 is triggered by SMCTGg_PTRG TR2 bit8 S20 Trigger Enable for Operati...

Page 405: ...r the SMC trigger group S1 triggered by SMCTGg_PTRG TR1 Bit Description 0 SMC 6 g 2 is not triggered by SMCTGg_PTRG TR1 1 SMC 6 g 2 is triggered by SMCTGg_PTRG TR1 bit1 S11 Trigger Enable for Operatio...

Page 406: ...Wp INITIAL_VALUE 0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME Reserved TR2 TR1 ACCESS_TYPE R0 WX R0 W R0 W PROT_TYPE Rp Wp INITIAL_VALUE 0 0 0 bit1 TR2 SMC Trigger 2 This bit triggers the SMC trigger group S...

Page 407: ...unters if enabled in SMCi_PTRGDL If the delay has elapsed or the delay is disabled the Count Enable SMCi_PWC CE bits of the selected SMC channels will be set and the operation starts PWM generation an...

Page 408: ...are Manual Document Number 002 04852 Rev G 407 CHAPTER 18 Sound Generator This chapter explains the functions and operations of the Sound Generator SG 1 Overview 2 Configuration 3 Operations 4 Registe...

Page 409: ...SGCCR PWM pulse generation counter Frequency counter Decrement counter Tone pulse counter Functions of Sound Generator Table 1 1 Functions of Sound Generator No Item Function 1 Operation clock Bus clo...

Page 410: ...t PWM pulse generator Reload Amplitude Data Register SGAR Frequency Counter Frequency Data Register SGFR Decrement counter Time Cycle Register SGTCR Toggle Flip flop Tone pulse counter Tone Output Num...

Page 411: ...one cycle TCn to the Time Cycle Register SGTCR Time cycle number to assert interrupts Nn to the Tone Output Number Register Amplitude Time Amplitude Data Register SGAR Frequency Data Register SGFR Tim...

Page 412: ...Data Register SGPCR Other information about Sound Generator control to the Sound Control Register SGCR The Sound Generator outputs the tone pulse signal and the amplitude data according to the settin...

Page 413: ...e length of a PWM cycle is programmable in the PWM Cycle Data Register SGPCR This length is based on the count of input clock The initial value is 256 input clock cycle SGPCR 0x00FF The value Amplitud...

Page 414: ...und Control Register SGCR is 0 the tone pulse signal is mixed with a PWM pulse and is output from the SGO pin And when the Tone output bit TONE of the Sound Control Register SGCR is 1 the tone pulse s...

Page 415: ...M cycle is a reference clock for a tone pulse signal or a mixed signal of the tone pulse signal and a PWM pulse signal and a PWM pulse signal To generate the same sound output both by the bus clock at...

Page 416: ...of SGDER TCRE SGDER IDRE SGDER PCRE1 and SGDER PCRE0 The transfer size of 3 bytes is regarded as 4 bytes 3 4 3 Transfer Byte Position in the DMA Transfer Intermediate Register SGDMAR The DMA transfer...

Page 417: ...24 SGDMAR 23 16 5 0 0 1 0 1 SGDMAR 31 24 6 1 0 1 0 2 SGDMAR 31 24 SGDMAR 23 16 7 0 1 1 0 2 SGDMAR 31 24 SGDMAR 23 16 8 1 1 1 0 4 SGDMAR 31 24 SGDMAR 23 16 SGDMAR 15 8 9 0 0 0 1 1 SGDMAR 31 24 10 1 0 0...

Page 418: ...r Update Enable Register SGDER When this transfer size 2 is not 4 bytes the transfer byte position is left aligned Table 3 2 The Relations between the Setting of the DMA Transfer Update Enable Registe...

Page 419: ...GDER IDRE SGDER PCRE1 and SGDER PCRE0 Do not care 3 4 4 DMA Transfer Image This section shows an example of DMA transfer image under the setting of DMA Transfer Update Enable Register SGDER SGDER ARE1...

Page 420: ...SGTCR 7 0 SGIDR 7 0 SGPCR 15 8 SGPCR 7 0 31 24 7 0 23 16 15 8 Sound Generator DMA transfer 1 1 SGIDR 7 0 1 31 24 7 0 23 16 15 8 SGAR 15 8 SGAR 7 0 SGFR 7 0 SGNR 7 0 SGTCR 7 0 SGIDR 7 0 SGPCR 15 8 SGPC...

Page 421: ...cle Data Register SGPCR Moreover set other information to the Sound Control Register SGCR to control the Sound Generator Initialize the Interrupt status bit SGCR INT and set the Interrupt enable bit S...

Page 422: ...uest PIRQ Tone pulse counter is 0x00 Decrement counter is 0x00 At the rising edge of SGO 7 Write 0 to the Start bit SGCR ST The Sound Generator keeps operating until the Busy status bit SGCR BUSY turn...

Page 423: ...e Start bit SGCR ST 4 The outputs of SGO and SGA start 5 The Tone pulse counter counts the number of tone pulses When the following conditions are satisfied the interrupt is generated Tone pulse count...

Page 424: ...ata Register SGAR Frequency Data Register SGFR Tone Output Number Register SGNR Time Cycle Register SGTCR Increase and Decrease Data Register SGIDR PWM Cycle Data Register SGPCR 7 1 SGO SGA output n 1...

Page 425: ...ster SGAR Frequency Data Register SGFR Tone Output Number Register SGNR Time Cycle Register SGTCR Increase and Decrease Data Register SGIDR and PWM Cycle Data Register SGPCR by software 1 Set only the...

Page 426: ...ites a register related to DMA in the Sound Generator The timing of the first interrupt with DMA is different from the flow by MCU The DMAC writes functional registers in the Sound Generator through t...

Page 427: ...e current tone cycle output is finished 11 13 The sound output starts because access with 4 byte size x2 is given on the DMA Transfer Intermediate Register SGDMAR This interrupt is asserted because th...

Page 428: ...writing 1 to Interrupt status clear bit SGCCR INTC Then the software configures the Sound Control Register SGCR in the needed mode and this must include the following bit operations DMA transfer start...

Page 429: ...GCR ST to stop outputting the sound 15 When above operation 14 was made within the following time the Nth DMA transfer doesn t come to the output of SGO and SGA The Sound Generator stops driving SGO a...

Page 430: ...te Register SGDMAR Increase and Decrease Data Register 2 bytes x2 DMA transfer 2 Within Frequency Data SGFR 1 x 1 PWM cycle DMA Transfer Intermediate Register SGDMAR Frequency Data Tone Output Number...

Page 431: ...not automatically updated 4 Software initialize Interrupt status bit SGCR INT by writing 1 to Interrupt status clear bit SGCCR INTC Then the software configures the Sound Control Register SGCR in the...

Page 432: ...the sound 16 When above operation 15 was made within the following time the Nth DMA transfer doesn t come to the output of SGO and SGA The Sound Generator stops driving SGO and SGA just before output...

Page 433: ...M cycle and the stop instruction is set as SGCR ST 0 the SGO and SGA are output 16 17 DMA Transfer Intermediate Register SGDMAR Frequency Data 1 bytes x1 DMA transfer 2 Within Frequency Data SGFR 1 x...

Page 434: ...are configures the Sound Control Register SGCR in the needed mode and this must include the following bit operations DMA transfer start interrupt setting enable bit SGCR DMA to 1 enabled Interrupt ena...

Page 435: ...driving SGO and SGA just before outputting the data of Nth DMA transfer The limit time Frequency Data Register SGFR 1 x 1 PWM cycle 4 The data of the Nth DMA transfer are written to the Sound Generat...

Page 436: ...If the current tone cycle is outputting the SGO and SGA output stops when the current tone cycle output is finished 14 17 The sound output starts because access with 4 byte size x2 is given on the DMA...

Page 437: ...writing 1 to Interrupt status clear bit SGCCR INTC Then the software configures the Sound Control Register SGCR in the needed mode and this must include the following bit operations DMA transfer start...

Page 438: ...pulse counter counts the number of tone pulses When the following conditions are satisfied the interrupt is generated Tone pulse counter is 0x00 Decrement counter is 0x00 At the rising edge of SGO 15...

Page 439: ...e from step 5 to 6 within the following time The limit time Frequency Data Register SGFR 1 x 1 PWM cycle The DMA transfer error means the occurrence of delay in the sound data setting It causes unstea...

Page 440: ...ps when the current tone cycle output is finished 15 17 The sound output starts because access with 4 byte size x2 is given on the DMA Transfer Intermediate Register SGDMAR This interrupt is asserted...

Page 441: ...writing 1 to Interrupt status clear bit SGCCR INTC Then the software configures the Sound Control Register SGCR in the needed mode and this must include the following bit operations DMA transfer start...

Page 442: ...or the access to DMA Transfer Intermediate Register SGDMAR 16 Repeat the step 15 to continue outputting the sound 17 When DMAC completes all DMA transfer with 4 byte size x2 M times it asserts an inte...

Page 443: ...e interrupt control bit and its factor is shown in the following table Table 3 3 The Interrupt Bit of Sound Generator and Its Factor During the tone pulses are counted when the count reaches the multi...

Page 444: ...4 7 SGPCR PWM Cycle Data Register 4 8 SGDMAR DMA Transfer Intermediate Register 4 9 SGCCR Interrupt Clear Register 4 10 The Meaning of the Register Bit Property Code Table 4 2 The Meaning of the Regi...

Page 445: ...ARE1 Amplitude data upper byte update enable bit This bit is to enable the update of the amplitude data upper byte of the Amplitude Data Register SGAR through the DMA Transfer Intermediate Register wh...

Page 446: ...te of the increase and decrease data of the Increase and Decrease Data Register SGIDR through the DMA Transfer Intermediate Register when in DMA transfer Bit Description 0 The update of the increase a...

Page 447: ...lue 0 0 0 0 0 0 0 0 bit15 Reserved Reserved bit Always write 0 to this bit The read value is 0 bit14 SRST Software reset bit This bit is used to issue a software reset in the Sound Generator When in t...

Page 448: ...This bit is valid only when the automatic increase decrease enable bit is set to enabled GEN 1 If this bit is changed during the operation it is reflected at the time when the value of Amplitude Data...

Page 449: ...e is 0 bit7 6 S1 S0 Operation clock select bits The combination of these bits controls the internal clock division to determine the bit rate on the output sound S1 S0 Description 0 0 The division rati...

Page 450: ...bit has no effect Bit Description Read Write 0 Sound Generator hasn t detected the end of tone pulses This bit is cleared under any of following conditions Software reset is set SRST 1 DMA transfer I...

Page 451: ...2 DMAC writes a value through DMA Transfer Intermediate Register SGDMAR When in decreasing the value of this register 0x0000 is the lower limit and the value doesn t roll over to 0xFFFF from it When i...

Page 452: ...tten either in the following ways 1 Software writes a value to this register 2 DMAC writes a value through DMA Transfer Intermediate Register SGDMAR Notes The number of PWM pulses is equal to SGFR 1 D...

Page 453: ...Initial value 0x00 bit7 0 SGNR Tone output number bits These bits store the reload value for the Tone pulse counter and the value is written either in the following ways 1 Software writes a value to t...

Page 454: ...s register 2 DMAC writes a value through DMA Transfer Intermediate Register SGDMAR Notes The number of pulses is equal to SGTCR 1 When SGTCR is 0x00 the automatic increase or decrease operation on the...

Page 455: ...crement for the Amplitude Data Register SGAR and the value is written either in the following ways 1 Software writes a value to this register 2 DMAC writes a value through DMA Transfer Intermediate Re...

Page 456: ...in 1PWM cycle and the value is written either in the following ways 1 Software writes a value to this register 2 DMAC writes a value through DMA Transfer Intermediate Register SGDMAR Notes The number...

Page 457: ...2 1 0 Field SGDMAR 7 0 Attribute W Initial value 0x00 bit31 0 SGDMAR DMA Transfer data bits This register is used to write the following registers Amplitude Data Register SGAR Frequency Data Register...

Page 458: ...R and individual registers SGAR SGFR SGNR SGTCR SGIDR SGPCR During operation in the case of changing a register value meet the following either conditions 1 Sound generator is in the stop state SGCR B...

Page 459: ...alue 0x00 bit 7 6 5 4 3 2 1 0 Field Reserved INTC Reserved Attribute W Initial value 0x00 0 0 Note Use 16 or 32 bit data access for the SGCCR register bit15 2 Reserved Reserved bits Always write 0 to...

Page 460: ...t Number 002 04852 Rev G 459 CHAPTER 19 Sound Waveform Generator This chapter explains the sound waveform generator 1 Overview 2 Configuration and Block Diagram 3 Operation of the Sound Waveform Gener...

Page 461: ...Code Modulation sound source XXXX internally by the SWFG expands it to 32 bits and outputs it AHB master interface The output data pattern can be selected by register settings XXXX_XXXX Upper and lowe...

Page 462: ...is section shows a block diagram of the sound waveform generator Figure 2 1 AHB Master controller Sound source Output AHB Slave controller Register configuration interface Module controller Registers...

Page 463: ...8 End idle time This function is not supported 4 8 Waveform Sound source waveform 4 7 Frequency Sound source frequency 4 7 Run time Time to generate a sound source of a specified frequency 4 7 Fade i...

Page 464: ...ware For details see 4 7 Notes Neither the start nor end idle times are included in the run time Fade in time and fade out time are both included in the run time 3 1 5 Fade In Time ATTACK Fade in time...

Page 465: ...1 6 Start sound source generation For details see WGCHSTART under 4 2 Notes Steps 1 through 4 of the above procedure can be performed in any sequence Enabling operation in step 5 of the above procedu...

Page 466: ...ion of a configured sound source by HW operation The sound source n 2 The sound source n 1 The sound source n 1 Notes Setting the next sound s sound source specifications after the previous sound sour...

Page 467: ...move overtone affections of sawtooth and square wave form See 4 7 in detail Figure 3 3 Cutoff Frequency 8 kHz Figure 3 4 Cutoff Frequency 5 kHz 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 x 10 4 100 90 80 7...

Page 468: ...or S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 467 Figure 3 5 Cutoff Frequency 2 kHz 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 x 10 4 100 90 80 70 60 50 40 30 20 10 0 10 filter3 frequen...

Page 469: ...T 23 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0...

Page 470: ...it0 CH0EN Channel 0 operation enable disable CHnEN n 0 to 4 Description 0 Stop operation 1 Enable operation Notes When operation is stopped SWFG stops sound source generation and output There is no so...

Page 471: ...ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved...

Page 472: ...e a previous sound source generation is in progress consecutive sound source generation starts when generation of the previous sound source is complete This bit is automatically cleared when the desir...

Page 473: ...16 BIT_NAME CH1ADD 7 0 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved Reserved Reserved CH0ADD 12 8 ACCESS_T...

Page 474: ...Rev G 473 bit15 13 Reserved This bit is reserved Always write 0 to this bit The read value is 0 bit12 0 CH0ADD Channel 0 output destination address Sets the Channel 0 output destination address as 13...

Page 475: ...16 BIT_NAME CH3ADD 7 0 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved Reserved Reserved CH2ADD 12 8 ACCESS_T...

Page 476: ...Rev G 475 bit15 13 Reserved This bit is reserved Always write 0 to this bit The read value is 0 bit12 0 CH2ADD Channel 2 output destination address Sets the Channel 2 output destination address as 13...

Page 477: ...rved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10...

Page 478: ...rved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved Reser...

Page 479: ...umber 002 04852 Rev G bit1 0 CH0MONO Channel 0 output data pattern CHnMONO 1 0 n 0 to 4 Description 00 Upper and lower 16 bits output the same data XXXX_XXXX 01 Only lower 16 bits of data are output 0...

Page 480: ...E Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved FSLEN 4 0 ACCESS_TYPE R0 W0 R0 W0 R0 W0 R W R W R W R W R W PROT_TYPE Wp INITIAL_VALUE 0 0 0 0...

Page 481: ...11 100ms 10000 125ms 10001 150ms 10010 200ms 10011 250ms 10100 300ms 10101 400ms 10110 500ms 10111 750ms 11000 1000ms 11001 1250ms 11010 1500ms 11011 2000ms 11100 2500ms 11101 3000ms 11110 3500ms 1111...

Page 482: ...Q 5 0 Frequency Hz Musical Scale 00 110 00 A2 01 116 54 A 2 02 123 47 B2 03 130 81 C3 04 138 59 C 3 05 146 83 D3 06 155 56 D 3 07 164 81 E3 08 174 61 F3 09 185 00 F 3 0A 196 00 G3 0B 207 65 G 3 0C 220...

Page 483: ...932 33 A 5 26 987 77 B5 27 1046 50 C6 28 1108 73 C 6 29 1174 66 D6 2A 1244 51 D 6 2B 1318 51 E6 2C 1396 91 F6 2D 1479 98 F 6 2E 1567 98 G6 2F 1661 22 G 6 30 1760 00 A6 31 1864 66 A 6 32 1975 53 B6 33...

Page 484: ...LUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved ITVAL2 4 0 ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0...

Page 485: ...ies a setting of 0 ms to 4 seconds ITVAL2 4 0 ITVAL1 4 0 Description 00000 0ms 00001 1ms 00010 2ms 00011 3ms 00100 4ms 00101 5ms 00110 7 5ms 00111 10ms 01000 15ms 01001 20ms 01010 25ms 01011 30ms 0110...

Page 486: ...0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved FILTER 1 0 ACCESS_TYPE R0 W0 R0 W...

Page 487: ...fies a setting of 1 ms to 1 second Set these bits to 00000 when fade in control is not used bit7 5 Reserved This bit is reserved Always write 0 to this bit The read value is 0 bit4 0 ATTACK Fade in ti...

Page 488: ...10100 300ms 10101 400ms 10110 500ms 10111 750ms 11000 to 11111 1000ms Notes Exercise caution concerning use when performing consecutive sound source generation See 3 1 5 3 1 6 When using fade in cont...

Page 489: ...eserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved Reserved Reserved Reserved Re...

Page 490: ...1 is written to this bit the set sound source specifications are initialized and sound source generation stops However this control does not initialize the source specification setting register but i...

Page 491: ...R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved Reserved Reserved CH4END CH3END CH2END CH1END CH0END ACCESS_TYP...

Page 492: ...el 0 sound source generation end interrupt enable CHnEND n 0 to 4 Description 0 Disable interrupts 1 Enable interrupts bit7 1 Reserved This bit is reserved Always write 0 to this bit The read value is...

Page 493: ...W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved Reserved Reserved CH4END CH3END CH2END CH1END CH0END ACCESS_TYPE R0...

Page 494: ...Interrupt bit7 1 Reserved This bit is reserved Always write 0 to this bit The read value is 0 This bit is read only and writing is prohibited Writing to this bit generates an SWFG AHB Slave interface...

Page 495: ...R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved Reserved Reserved CH4END CH3END CH2END CH1END CH0END ACCESS_TYPE...

Page 496: ...ot have any effect on operation 1 Clear interrupts bit7 1 Reserved This bit is reserved Always write 0 to this bit The read value is 0 bit0 AHBERR SWFG AHB MASTER INTERFACE bus error interrupt clear E...

Page 497: ...rved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reser...

Page 498: ...AHBSERR SWFG AHB Slave Interface access error information indication Bits Description 00 There is no error 01 Address error 10 Write access to Read Only register 11 Access size error Notes This bit i...

Page 499: ...are Manual Document Number 002 04852 Rev G CHAPTER 20 Sound Mixer This chapter explains the sound mixer 1 Overview 2 Configuration and Block Diagram 3 Operation of the Sound Mixer 4 Registers 5 Append...

Page 500: ...have a fixed connection to WFG0 to 4 It should be noted that there may be specification limits on specific models The 44 1 kHz input sampling rate can be applied to only one of the input channels PMI...

Page 501: ...nterface BUFFER interface PMIS0 PMIS1 Input PMIS2 BUFFER 0 4 PMIS3 PMIS4 AHB LITE Notes The mixing section is equipped with functions for use by volume effects volume control mute fade in fade out eff...

Page 502: ...9 Start sound source input Notes The settings in steps 3 4 and 7 are not required for sound source input channels WFG0 through 4 Also other settings equivalent to these settings are not configured Con...

Page 503: ...tion will perform fade in control of the fade gain from 96 dB to 0 dB However this initialization operation is not necessarily required for fade in following fade out This is because fade out causes g...

Page 504: ...ation is in progress and settings are immediately reflected in operation For information about register settings see 4 6 4 7 and 4 8 For details about gain for volume control see 5 1 3 2 2 Mute Output...

Page 505: ...es input 32 bit stereo sound source Monaural processing R Right side mixing Mixes by converting to 32 bit data Upper 16 bits ALL 0 Lower 16 bits Monaural sound source Monaural processing L Left side m...

Page 506: ...on on the AHB Master Interface of the sound mixer The sound mixer interrupt enable setting interrupt clear control and status indication 3 5 Data Request Control Mixer macros generate two types of dat...

Page 507: ...HB slave interface groups for WFG interfacing and for CPU interfacing AHB Slave interface specifications are shown in Table 3 3 and Table 3 4 3 7 1 AHB Slave Interface CPU DMA Table 3 3 AHB Slave inte...

Page 508: ...it Notes When an ERROR response is received by transfer control from the CPU interface an error response is transferred to the CPU interface Information about the operation when an error response is r...

Page 509: ...mpling rate Conversion is by up sampling along with processing by an FIR filter to dampen high frequency noise and prevent changes in sound quality However down sampling is performed in the case of a...

Page 510: ...22 21 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0...

Page 511: ...PMISn input valid Notes PMISn bit must not be changed from 0 to 1 when DMAENCHn bit of MXDRQCTRL register is 1 bit4 WFG4 WFG4 input setting bit3 WFG3 WFG3 input setting bit2 WFG2 WFG2 input setting b...

Page 512: ...9 18 17 16 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_O...

Page 513: ...re 1 number of data items to the output destination Notes These bits can be set at the initialization After that it should not be changed bit7 3 Reserved This bit is reserved Always write 0 to this bi...

Page 514: ...8 17 16 BIT_NAME Reserved Reserved Reserved Reserved FESTCH4 3 0 ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R W R W R W R W PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAM...

Page 515: ...1 8 FESTCH2 Data transfer to PMIS2 request assert threshold setting bit7 4 FESTCH1 Data transfer to PMIS1 request assert threshold setting bit3 0 FESTCH0 Data transfer to PMIS0 request assert threshol...

Page 516: ...eserved Reserved Reserved Reserved PMIS4FREQ 2 0 ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R W R W R W PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 1 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved PMI...

Page 517: ...bit is reserved Always write 0 to this bit The read value is 0 bit2 0 PMIS0FREQ Input sampling frequency to PMIS0 PMISnFREQ 2 0 n 0 to 4 Description 000 96KHz 001 48KHz 010 24KHz 011 12KHz 100 8KHz 1...

Page 518: ...23 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0...

Page 519: ...S1MONO PMIS1 sound source processing mode setting bit1 0 PMIS0MONO PMIS0 sound source processing mode setting PMISnMONO 1 0 n 0 to 4 Description 00 Stereo processing 01 Monaural process R Upper 16 bit...

Page 520: ...VOL 7 0 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE Wp INITIAL_VALUE 1 1 1 0 0 1 1 1 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME WFG1VOL 7 0 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TY...

Page 521: ...ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE Wp INITIAL_VALUE 1 1 1 0 0 1 1 1 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME PMIS0VOL 7 0 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE Wp...

Page 522: ..._NAME MXDVOL 7 0 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE Wp INITIAL_VALUE 1 1 1 0 0 1 1 1 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME PMIS4VOL 7 0 ACCESS_TYPE R W R W R W R W R W R W R W R...

Page 523: ...ved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved Reserv...

Page 524: ...PMIS1 input sound source MUTE setting bit5 PMIS0MUTE PMIS0 input sound source MUTE setting PMISnMUTE n 0 to 4 Description 0 Disable mute 1 Enable mute bit4 WFG4MUTE WFG4 input sound source MUTE settin...

Page 525: ...d Reserved Reserved WFG1FADEIN 4 0 ACCESS_TYPE R0 W0 R0 W0 R0 W0 R W R W R W R W R W PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved Reserved Reserved WFG...

Page 526: ...t15 13 Reserved This bit is reserved Always write 0 to this bit The read value is 0 bit12 8 WFG0FADEOUT WFG0 fade out time setting bit7 3 Reserved This bit is reserved Always write 0 to this bit The r...

Page 527: ...d Reserved Reserved WFG3FADEIN 4 0 ACCESS_TYPE R0 W0 R0 W0 R0 W0 R W R W R W R W R W PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved Reserved Reserved WFG...

Page 528: ...t15 13 Reserved This bit is reserved Always write 0 to this bit The read value is 0 bit12 8 WFG2FADEOUT WFG2 fade out time setting bit7 5 Reserved This bit is reserved Always write 0 to this bit The r...

Page 529: ...Reserved Reserved PMIS0FADEIN 4 0 ACCESS_TYPE R0 W0 R0 W0 R0 W0 R W R W R W R W R W PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved Reserved Reserved WFG...

Page 530: ...it15 13 Reserved This bit is reserved Always write 0 to this bit The read value is 0 bit12 8 WFG4FADEOUT WFG4 fade out time setting bit7 5 Reserved This bit is reserved Always write 0 to this bit The...

Page 531: ...Reserved Reserved PMIS2FADEIN 4 0 ACCESS_TYPE R0 W0 R0 W0 R0 W0 R W R W R W R W R W PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved Reserved Reserved PMIS...

Page 532: ...15 13 Reserved This bit is reserved Always write 0 to this bit The read value is 0 bit12 8 PMIS1FADEOUT PMIS1 fade out time setting bit7 5 Reserved This bit is reserved Always write 0 to this bit The...

Page 533: ...7 16 BIT_NAME Reserved Reserved Reserved PMIS4FADEIN 4 0 ACCESS_TYPE R0 W0 R0 W0 R0 W0 R W R W R W R W R W PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved...

Page 534: ...ade in time setting bit15 13 Reserved This bit is reserved Always write 0 to this bit The read value is 0 bit12 8 PMIS3FADEOUT PMIS3 fade out time setting bit7 5 Reserved This bit is reserved Always w...

Page 535: ...R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved Reserved Reserved MXDFADEOUT 4 0 ACCESS_TYPE R0 W0 R0 W0...

Page 536: ...UE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved MXDFADEEN 1 0 PMIS4FADEEN 1 0 PMIS3FADEEN 1 0 ACCESS_TYPE R0 W0 R0 W0 R W R W R W R W R W R W PROT_TYPE Wp INITIAL_VALU...

Page 537: ...PMIS1FADEEN PMIS1 fade in out operation setting bit11 10 PMIS0FADEEN PMIS0 fade in out operation setting PMISnFADEEN 1 0 n 0 to 4 Description 00 No fade in fade out 01 Setting prohibited 10 Enable fa...

Page 538: ...17 16 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSE...

Page 539: ...0 Not under initialization Does not have any effect on operation 1 Initialization wait Initialize buffer This bit automatically cleared to 0 following initialization Note PMISn input buffer initializ...

Page 540: ...1 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0...

Page 541: ...state initialization PMISnCLR n 0 to 4 Description Read Write 0 Not under initialization Does not have any effect on operation 1 Initialization wait Initialize fade state This bit automatically cleare...

Page 542: ...Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R W R W R W R W R W PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Re...

Page 543: ...nterrupt setting PMISnDMAERR n 0 to 4 Description 0 Disable interrupts 1 Enable interrupts bit23 13 Reserved This bit is reserved Always write 0 to this bit The read value is 0 bit12 PMIS4BUFOVFL PMIS...

Page 544: ...S2 data transfer request interrupt setting bit1 PMIS1BUFDREQ PMIS1 data transfer request interrupt setting bit0 PMIS0BUFDREQ PMIS0 data transfer request interrupt setting PMISnBUFDREQ n 0 to 4 Descrip...

Page 545: ...Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R WX R WX R WX R WX R WX PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved Reserved Reserved PMIS4...

Page 546: ...IS0DMAERR PMIS0DMA transfer error indication PMISnDMAERR n 0 to 4 Description 0 No error no transfer request 1 Error transfer request present Notes This bit is read only and writing is prohibited Writ...

Page 547: ...nly and writing is prohibited Writing to this bit generates a sound mixer AHB Slave interface access error bit4 PMIS4BUFDREQ PMIS4 data transfer request indication bit3 PMIS3BUFDREQ PMIS3 data transfe...

Page 548: ...erved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE RX W0 RX W0 RX W0 RX W RX W RX W RX W RX W PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved...

Page 549: ...PMISnDMAERR n 0 to 4 Description 0 Does not have any effect on operation 1 Clear interrupts bit23 13 Reserved This bit is reserved Always write 0 to this bit The read value is 0 bit12 PMIS4BUFOVFL PMI...

Page 550: ...errupt clear bit2 PMIS2BUFDREQ PMIS2 data transfer request interrupt clear bit1 PMIS1BUFDREQ PMIS1 data transfer request interrupt clear bit0 PMIS0BUFDREQ PMIS0 data transfer request interrupt clear P...

Page 551: ...R WX R WX PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved PMIS1CNT 5 0 ACCESS_TYPE R0 W0 R0 W0 R WX R WX R WX R WX R WX R WX PROT_TYPE Wp INIT...

Page 552: ...This bit is read only and writing is prohibited Writing to this bit generates a sound mixer AHB Slave Interface access error bit23 20 Reserved This bit is reserved Always write 0 to this bit The read...

Page 553: ...Slave Interface access error bit7 5 Reserved This bit is reserved Always write 0 to this bit The read value is 0 This bit is read only and writing is prohibited Writing to this bit generates a sound m...

Page 554: ...rved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reser...

Page 555: ...access error bit7 6 Reserved This bit is reserved Always write 0 to this bit The read value is 0 This bit is read only and writing is prohibited Writing to this bit generates a sound mixer AHB Slave i...

Page 556: ...R WX R WX R WX R WX PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME PMIS1CNT 3 0 PMIS0CNT 3 0 ACCESS_TYPE R WX R WX R WX R WX R WX R WX R WX R WX PROT_TYPE Wp INIT...

Page 557: ...Interface access error bit7 5 Reserved This bit is reserved Always write 0 to this bit The read value is 0 This bit is read only and writing is prohibited Writing to this bit generates a sound mixer...

Page 558: ...d Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME...

Page 559: ...52 Rev G bit5 0 OUTCNT 5 0 Output buffer used volume indication Bit 5 0 Description 000000 Buffer is empty 000001 to 111111 Output buffer used volume Notes This bit is read only and writing is prohibi...

Page 560: ...eserved CNTREGERR 1 0 PMIS4ERR 1 0 PMIS3ERR 1 0 ACCESS_TYPE R0 W0 R0 W0 R WX R WX R WX R WX R WX R WX PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME PMIS2ERR 1 0...

Page 561: ...PMIS2 transfer access error information indication bit13 12 PMIS1ERR 1 0 AHB Slave interface PMIS1 transfer access error information indication bit11 10 PMIS0ERR 1 0 AHB Slave interface PMIS0 transfer...

Page 562: ...Address error 10 Write access to Read Only register 11 Access size error Notes This bit is read only and writing is prohibited Writing to this bit generates a Mixer AHB Slave Interface access error E...

Page 563: ...0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME WFGnDADR 23 16 ACCESS_TYPE R0 W R0 W R0 W R0 W R0 W R0 W R0 W R0 W PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_N...

Page 564: ...to 15 31 24 ACCESS_TYPE R0 W R0 W R0 W R0 W R0 W R0 W R0 W R0 W PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME PMIS n DADR0 to 15 23 16 ACCESS_TYPE R0 W R0 W R0...

Page 565: ...001 96 0 0 000016 00001010 96 0 0 000016 00001011 96 0 0 000016 00001100 96 0 0 000016 00001101 96 0 0 000016 00001110 96 0 0 000016 00001111 96 0 0 000016 00010000 96 0 0 000016 00010001 96 0 0 00001...

Page 566: ...0025 00110000 91 5 0 000027 00110001 91 0 0 000028 00110010 90 5 0 000030 00110011 90 0 0 000032 00110100 89 5 0 000033 00110101 89 0 0 000035 00110110 88 5 0 000038 00110111 88 0 0 000040 00111000 87...

Page 567: ...0251 01011000 71 5 0 000266 01011001 71 0 0 000282 01011010 70 5 0 000299 01011011 70 0 0 000316 01011100 69 5 0 000335 01011101 69 0 0 000355 01011110 68 5 0 000376 01011111 68 0 0 000398 01100000 67...

Page 568: ...2512 10000000 51 5 0 002661 10000001 51 0 0 002818 10000010 50 5 0 002985 10000011 50 0 0 003162 10000100 49 5 0 003350 10000101 49 0 0 003548 10000110 48 5 0 003758 10000111 48 0 0 003981 10001000 47...

Page 569: ...5119 10101000 31 5 0 026607 10101001 31 0 0 028184 10101010 30 5 0 029854 10101011 30 0 0 031623 10101100 29 5 0 033497 10101101 29 0 0 035481 10101110 28 5 0 037584 10101111 28 0 0 039811 10110000 27...

Page 570: ...11 12 0 0 251189 11010000 11 5 0 266073 11010001 11 0 0 281838 11010010 10 5 0 298538 11010011 10 0 0 316228 11010100 9 5 0 334965 11010101 9 0 0 354813 11010110 8 5 0 375837 11010111 8 0 0 398107 110...

Page 571: ...1101110 3 5 1 496236 11101111 4 0 1 584893 11110000 4 5 1 678804 11110001 5 0 1 778279 11110010 5 5 1 883649 11110011 6 0 1 995262 11110100 6 5 2 113489 11110101 7 0 2 238721 11110110 7 5 2 371374 111...

Page 572: ...ms 24000 sample 01010 600ms 28800 sample 01011 700ms 33600 sample 01100 800ms 38400 sample 01101 900ms 43200 sample 01110 1000ms 48000 sample 01111 1100ms 52800 sample 10000 1200ms 57600 sample 10001...

Page 573: ...to change sampling rate See 3 10 2 of the description of FIR digital filter No Sampling frequency Cutoff frequency Remark 1 44kHz 17kHz Figure 5 1 2 24kHz 11kHz Figure 5 2 3 12kHz 5kHz Figure 5 3 4 8...

Page 574: ...2 Filter No 2 Figure 5 3 Filter No 3 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 x 10 4 100 90 80 70 60 50 40 30 20 10 0 10 filter24 frequency response Frequency Hz gain dB 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6...

Page 575: ...4 Filter No 4 Figure 5 5 Filter No 5 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6 1 8 2 x 10 4 100 90 80 70 60 50 40 30 20 10 0 10 filter08 frequency response Frequency Hz gain dB 0 0 2 0 4 0 6 0 8 1 1 2 1 4 1 6...

Page 576: ...4852 Rev G 575 CHAPTER 21 Ethernet MAC This chapter explains the function and operation of the Ethernet MAC module 1 Overview 2 Configuration and Block Diagram 3 Operation of the Ethernet MAC 4 Regist...

Page 577: ...re C comparisons full duplex 100Mbit s operation AMBA AXI Master Interface 32 bit address width 64 bit data width Acronyms and Abbreviations Acronym Description BD Buffer Descriptor CBS Credit Based S...

Page 578: ...cronym Description SGMII Serial Gigabit Media Independent Interface SNAP Subnetwork Access Protocol SOF Start Of Frame TCP Transfer Control Protocol TS Timestamp TSU Timestamp Unit UDP User Datagram P...

Page 579: ...al FIFO Interface Transmitter MAC Transmitter TX Packet Buffer Receiver MAC Receiver RX Packet Buffer Specific Address Filters Screener 1 Screener 2 RX Packet Buffer Memory TX Packet Buffer Memory IEE...

Page 580: ...e The Ethernet MAC s AXI master interface provides separate data and address connections for Reads and Writes which allow simultaneous bidirectional data transfers The Ethernet MAC supports multiple o...

Page 581: ...sence the packet buffer DMA will start behaving in a similar way to the internal FIFO DMA mode when partial store and forward is enabled Information regarding this behavior is described in section Rec...

Page 582: ...ery descriptor will be 128 bits wide when descriptor time capture mode is enabled The following description details the functionality of Word 0 and Word 1 Each list entry consists of the same first tw...

Page 583: ...ry Software has to clear this bit before the buffer can be used again Word 1 31 Global all ones broadcast address detected 30 Multicast hash match 29 Unicast hash match 28 External address match 27 Un...

Page 584: ...his bit will be set if the second VLAN tag has a Type ID of 8100h and a null VLAN identifier 19 17 VLAN priority only valid if bit 21 is set 000 Priority 0 lowest BK Background 001 Priority 1 BE Best...

Page 585: ...s before reception is enabled ETHERNETn_network_control 2 1 Once reception is enabled any writes to the RX Buffer Queue Base Address register are ignored When read it will return the current pointer p...

Page 586: ...resource next becomes available This may lead to an eventual packet buffer overflow if packets continue to be received when bit 0 Used bit of the receive buffer descriptor remains set Note that after...

Page 587: ...have the same number of words To summarize Every descriptor will be 64 bits wide when descriptor time capture mode is disabled Every descriptor will be 128 bits wide when descriptor time capture mode...

Page 588: ...identified as VLAN SNAP or IP 101 Non supported packet fragmentation occurred For IPv4 packets the IP checksum was generated and inserted 110 Packet type detected was not TCP or UDP TCP UDP checksum...

Page 589: ...sabled ETHERNETn_network_control 3 0 the transmit buffer queue pointer resets to point to the address indicated by the TX Buffer Queue Base Address register Note that disabling receive does not have t...

Page 590: ...via bits 26 and 25 of the DMA Configuration register Bit 26 will control the TX and bit 25 the RX For RX the data to burst is padded with 0 s up to the burst boundary defined by burst length For TX t...

Page 591: ...rflow will occur An overflow will also occur if the limit of 256 packets is breached The size of the RX Packet Buffer Memory is 4 Kbytes Transmit Packet Buffer The Transmit Packet Buffer TX Packet Buf...

Page 592: ...ed from TX Packet Buffer Memory to make room for a new frame to be fetched from system memory In partial store and forward mode a trigger is sent across to the MAC Transmitter as soon as sufficient pa...

Page 593: ...RNETn_network_control 9 The Ethernet MAC DMA will need to identify the highest available queue for transmit from when the start bit in the Network Control register is written to and the TX is in a hal...

Page 594: ...equal to the COMPARE value A 16 bit word comparison is done The byte at the OFFSET number of bytes from the index start is compared through bits 15 8 of the configured VALUE and MASK The OFFSET can be...

Page 595: ...least 96 bit times apart to guarantee the Interpacket Gap If the collision signal is asserted during transmission the transmitter will transmit a jam sequence of 32 bits taken from the data register a...

Page 596: ...uence Errors statistics register will still be incremented Additionally if configured to use the Ethernet MAC DMA and not enabled for jumbo frames mode then bit 13 of the receive buffer descriptor Wor...

Page 597: ...buffer descriptor gives an indication if the Ethernet MAC was able to verify the checksums There is also an indication if the frame had SNAP encapsulation These indication bits will replace the Type...

Page 598: ...dress filters is four Each specific address filter consists of two registers Specific Address Bottom i register and Specific Address Top i register Specific Address Bottom i register stores the first...

Page 599: ...pe ID the Type ID Match 1 register must be set up Type ID Match 1 0x0A8 80004321h 3 5 1 Broadcast Address Frames with the broadcast address of FFFFFFFFFFFFh are stored to memory only if the no_broadca...

Page 600: ...ation register 3 5 4 Disable Copy of Pause Frames Pause frames can be prevented from being written to memory by setting the disable copying of pause frames control bit 23 in the Network Configuration...

Page 601: ...hen Sync and Delay_Req messages are sent and received The timestamp is taken when the message timestamp point passes the clock timestamp point For Ethernet the message timestamp point is the SFD and t...

Page 602: ...h DA Octets 0 5 SA Octets 6 11 Type Octets 12 13 0800h IP stuff Octets 14 22 UDP Octet 23 11h IP stuff Octets 24 29 IP DA Octets 30 32 E00001h IP DA Octet 33 81h or 82h or 83h or 84h source IP port Oc...

Page 603: ...ersion 2 UDP IPv4 format Preamble SFD 55555555555555D5h DA Octets 0 5 SA Octets 6 11 Type Octets 12 13 0800h IP stuff Octets 14 22 UDP Octet 23 11h IP stuff Octets 24 29 IP DA Octets 30 33 E0000181h s...

Page 604: ...xample of a Sync frame in the IEEE Std 1588 version 2 Ethernet multicast format For the multicast address 011B19000000h Sync and Delay_Req frames are recognized depending on the message type field 00h...

Page 605: ..._clk There will be no more than 1 clock cycle of inaccuracy In the best case the SOF event which is in the TX RX clock domain just meets the setup time of the TSU clock domain at the input to the firs...

Page 606: ...us the value in IEEE 1588 Timer Nanoseconds register each clock cycle The IEEE 1588 Timer Nanoseconds register allows a resolution of approximately 15 femtoseconds 1ns 65536 Alternative Increment Mode...

Page 607: ...or if it matches the reserved address of 0180C2000001h It must also have the MAC control frame Type ID of 8808h and have the pause opcode of 0001h Pause frames that have FCS or other errors will be tr...

Page 608: ...Control register When this bit is set the Ethernet MAC will match either classic IEEE Std 802 3 pause frames or PFC priority based pause frames Once a priority based pause frame has been received and...

Page 609: ...ster A Type ID of 8808h MAC control frame A pause opcode of 0101h A priority enable vector taken from the Transmit PFC Pause register 8 pause quanta in 4 registers ETHERNETn_tx_pause_quantum ETHERNETn...

Page 610: ...led on the MII transmit path by asserting 0x01 on TXD with TX_EN low and TX_ER high 5 A PHY on seeing LPI requested on MII will send the sleep signal before going quiet After going quiet it will perio...

Page 611: ...t and must be less than the value of the portTransmitRate When this queue is transmitting the credit counter is decremented at the rate of sendSlope which is defined as the portTransmitRate idleSlope...

Page 612: ...n_phy_management Receive Pause Quantum Register ETHERNETn_pause_time Transmit Pause Quantum Register ETHERNETn_tx_pause_quantum Transmit Pause Quantum 1 Register ETHERNETn_tx_pause_quantum1 Transmit P...

Page 613: ...at all ones when they count to their maximum value They should be read frequently enough to prevent loss of data The receive statistics registers are only incremented when receive enable bit ETHERNETn...

Page 614: ...ts_rxed_top Frames Received Register ETHERNETn_frames_rxed_ok Broadcast Frames Received Register ETHERNETn_broadcast_rxed Multicast Frames Received Register ETHERNETn_multicast_rxed Pause Frames Recei...

Page 615: ...s Register ETHERNETn_tsu_peer_tx_nsec PTP Peer Event Frame Received Seconds 31 0 Register ETHERNETn_tsu_peer_rx_sec PTP Peer Event Frame Received Nanoseconds Register ETHERNETn_tsu_peer_rx_nsec Receiv...

Page 616: ...ERNETn_screening_type_1_register_13 Screening Type 1 Register 14 ETHERNETn_screening_type_1_register_14 Screening Type 1 Register 15 ETHERNETn_screening_type_1_register_15 Screening Type 2 Register 0...

Page 617: ...type2_compare_0_word_1 Type2 Compare Word 0 1 Register ETHERNETn_type2_compare_1_word_0 Type2 Compare Word 1 1 Register ETHERNETn_type2_compare_1_word_1 Type2 Compare Word 0 2 Register ETHERNETn_type2...

Page 618: ...9 Register ETHERNETn_type2_compare_19_word_0 Type2 Compare Word 1 19 Register ETHERNETn_type2_compare_19_word_1 Type2 Compare Word 0 20 Register ETHERNETn_type2_compare_20_word_0 Type2 Compare Word 1...

Page 619: ...9 Register ETHERNETn_type2_compare_29_word_1 Type2 Compare Word 0 30 Register ETHERNETn_type2_compare_30_word_0 Type2 Compare Word 1 30 Register ETHERNETn_type2_compare_30_word_1 Type2 Compare Word 0...

Page 620: ...Reserved store_udp_ offset Reserved ptp_unicast _ena tx_lpi_en flush_rx_pkt _clk transmit_pfc _priority_ba sed_pause_ frame pfc_enable ACCESS_TYPE R0 WX R W R W0 R W R W R0 W R0 W1S R W PROT_TYPE Wp I...

Page 621: ...operation 1 The upper 16 bits of the CRC of every received frame are replaced with the offset from start of frame to the beginning of the UDP or TCP header The lower 16 bits of the CRC are replaced wi...

Page 622: ...at was captured as the receive frame passed the message time stamp point bit14 stats_read_snap Read snapshot Bit Description 0 The current value of the statistics register will be read back 1 The snap...

Page 623: ...o effect 1 Clears all statistics registers Cleared by hardware bit4 man_port_en Management port enable Bit Description 0 Disable management ports MDIO is forced to High Z and MDC to 0 1 Enable managem...

Page 624: ..._OFFSET 23 22 21 20 19 18 17 16 BIT_NAME disable_cop y_of_pause _frames data_bus_width 1 0 mdc_clock_division 2 0 fcs_remove length_field _error_fram e_discard ACCESS_TYPE R W R W R W R W R W PROT_TYP...

Page 625: ...ror statistics will still be collected for frames with bad FCS and FCS status will be recorded in frame s DMA descriptor bit25 Reserved Read always returns written value Write always 0 bit24 receive_c...

Page 626: ...ngth indicated will be reduced by four bytes in this mode Bit Description 0 Disable 1 Enable bit16 length_field_error_frame_discard Length field error frame discard Setting this bit causes frames with...

Page 627: ...it Description 0 Unicast frames will not be accepted 1 Unicast frames will be accepted when the 6 bit hash function of the destination address points to a bit that is set in the Hash register bit6 mul...

Page 628: ...ed frames will be discarded 1 Only VLAN tagged frames will be passed to the address matching logic bit1 full_duplex Full duplex Bit Description 0 Setting not allowed 1 Full duplex mode The transmit bl...

Page 629: ...18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0 BIT_OFFSET 7 6 5 4 3 2 1 0 B...

Page 630: ...rity Based Pause has been negotiated bit5 3 Reserved Always read 0 Writing has no effect bit2 man_done Management done When this bit is set it means PHY management logic is idle i e has completed bit1...

Page 631: ..._on_err ACCESS_TYPE R0 WX R W R W R W R0 WX R W R W0 R W PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME rx_buf_size 7 0 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VAL...

Page 632: ...t_rx Force maximum length bursts on RX Bit Description 0 Maximum length bursts are not forced 1 Force max length bursts on RX Force the RX DMA to always issue maximum length bursts on EOP end of packe...

Page 633: ...s for transmit frames bit10 tx_pbuf_size Transmitter packet buffer memory size select This bit selects the amount of memory used for the transmit packet buffer The reset value of 1 represents the maxi...

Page 634: ...ons and only used where space and data size allow and respecting AXI burst boundary rules Bits Description 1xxxx Attempt to use bursts with up to 16 data transfers 01xxx Attempt to use bursts with up...

Page 635: ...11 10 9 8 BIT_NAME Reserved resp_not_ok ACCESS_TYPE R0 WX R W1C PROT_TYPE Wp INITIAL_VALUE 0x00 0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME late_collisio n_occurred transmit_un der_run transmit_co mplete am...

Page 636: ...e This bit is set when a frame has been transmitted Cleared by writing 1 to this bit bit4 amba_error Transmit frame corruption due to AMBA AXI errors Set if an error occurs whilst midway through readi...

Page 637: ...y through the buffer descriptor queue checking the used bits In terms of AMBA AXI operation the receive descriptors are read from memory using a single 32 bit AXI access Since the datapath is 64 bit w...

Page 638: ...CHAPTER 21 Ethernet MAC S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 637 bit1 0 Reserved Always read 0 Writing has no effect...

Page 639: ...ion of the descriptor currently being accessed Since the Ethernet MAC DMA handles two frames at once this may not necessarily be pointing to the current frame being transmitted In terms of AMBA AXI op...

Page 640: ...3200 Series Hardware Manual Document Number 002 04852 Rev G 639 bit31 2 dma_tx_q_ptr Transmit buffer queue base address Start address of transmit buffer queue in system memory bit1 0 Reserved Always r...

Page 641: ...TIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME Reserved resp_not_o k receive_ove rrun frame_re...

Page 642: ...ailable Buffer not available An attempt was made to get a new buffer and the pointer indicated that it was owned by the processor The RX DMA will reread the pointer each time an end of frame is receiv...

Page 643: ...LE NUMERIC_TYPE OTHER BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME Reserved tsu_timer_c omparison_i nterrupt Reserved receive_lpi_ indication_s tatus_bit_ch ange tsu_second s_register_i ncrement ptp_pd...

Page 644: ...cation_status_bit_change Receive LPI Indication Status Bit change Bit Description 0 Interrupt de asserted 1 Interrupt asserted Indicates that Receive LPI Indication Status bit has changed bit26 tsu_se...

Page 645: ...Req frame received Bit Description 0 Interrupt de asserted 1 Interrupt asserted Indicates a PTP Delay_Req frame has been received bit17 15 Reserved Writing has no effect These bits will read 111 if bi...

Page 646: ...serted 1 Interrupt asserted Set if an error occurs whilst midway through reading transmit frame from system memory including BRESP errors and buffers exhausted mid frame if the buffers run out during...

Page 647: ...omplete Receive complete Bit Description 0 Interrupt de asserted 1 Interrupt asserted Set when a frame has been stored in memory bit0 management_frame_sent Management frame sent Bit Description 0 Inte...

Page 648: ...able_ptp _pdelay_res p_frame_re ceived enable_ptp _pdelay_re q_frame_re ceived enable_ptp _sync_fram e_transmitt ed enable_ptp _delay_req _frame_tran smitted enable_ptp _sync_fram e_received enable_pt...

Page 649: ...lay_Req frame transmitted interrupt bit23 enable_ptp_pdelay_resp_frame_received Enable PTP Pdelay_Resp frame received Always read 0 Writing 1 enables PTP Pdelay_Resp frame received interrupt bit22 ena...

Page 650: ...9 8 Reserved Always read 0 Writing has no effect bit7 enable_transmit_complete Enable Transmit complete Always read 0 Writing 1 enables Transmit complete interrupt bit6 enable_amba_error Enable Transm...

Page 651: ...y_res p_frame_re ceived disable_ptp _pdelay_re q_frame_re ceived disable_ptp _sync_fram e_transmitt ed disable_ptp _delay_req _frame_tran smitted disable_ptp _sync_fram e_received disable_ptp _delay_r...

Page 652: ...1 disables PTP Pdelay_Req frame transmitted interrupt bit23 disable_ptp_pdelay_resp_frame_received Disable PTP Pdelay_Resp frame received Writing 1 disables PTP Pdelay_Resp frame received interrupt bi...

Page 653: ...terrupt bit9 8 Reserved Always read 0 Writing has no effect bit7 disable_transmit_complete Disable Transmit complete Writing 1 disables Transmit complete interrupt bit6 disable_amba_error Disable Tran...

Page 654: ...mask wol_event_r eceived_ma sk rx_lpi_indic ation_mask tsu_second s_register_i ncrement_ mask ptp_pdelay_ resp_frame _transmitte d_mask ptp_pdelay_ req_frame_t ransmitted_ mask ACCESS_TYPE R0 WX R WX...

Page 655: ...ption 0 Interrupt is enabled 1 Interrupt is disabled bit27 rx_lpi_indication_mask A read of this register returns the value of the RX LPI indication mask A write to this register directly affects the...

Page 656: ..._pdelay_req_frame_received_mask PTP Pdelay_Req frame received mask A read of this register returns the value of the PTP Pdelay_Req frame received mask A write to this register directly affects the sta...

Page 657: ...he corresponding bit in the interrupt status register causing an interrupt to be generated if a 1 is written Bit Description 0 Interrupt is enabled 1 Interrupt is disabled bit16 pcs_auto_negotiation_c...

Page 658: ...t status register causing an interrupt to be generated if a 1 is written Bit Description 0 Interrupt is enabled 1 Interrupt is disabled bit10 receive_overrun_interrupt_mask receive overrun interrupt m...

Page 659: ...ister directly affects the state of the corresponding bit in the interrupt status register causing an interrupt to be generated if a 1 is written Bit Description 0 Interrupt is enabled 1 Interrupt is...

Page 660: ...t0 management_done_interrupt_mask management done interrupt mask A write to this register directly affects the state of the corresponding bit in the interrupt status register causing an interrupt to b...

Page 661: ...ifted back to their original locations For a read operation the data bits will be updated with data read from the PHY It is important to write the correct values to the register to ensure a valid PHY...

Page 662: ...peration Bits Description 00 Reserved 01 Write operation 10 Read operation 11 Reserved bit27 23 phy_address PHY address PHY address bit22 18 register_address Register address Specifies the register in...

Page 663: ...ESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME quantum...

Page 664: ...CESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0xFF BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME quantum_p1 23 16 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0xFF BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME qua...

Page 665: ...T_TYPE Wp INITIAL_VALUE 0 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved dma_tx_cutthru_...

Page 666: ...HAPTER 21 Ethernet MAC S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 665 bit10 0 dma_tx_cutthru_threshold TX partial store and forward threshold Watermark value This value must be 0x1...

Page 667: ...PROT_TYPE Wp INITIAL_VALUE 0 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved dma_rx_cutth...

Page 668: ...CHAPTER 21 Ethernet MAC S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 667 bit8 0 dma_rx_cutthru_threshold RX partial store and forward threshold Watermark value...

Page 669: ...ved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME j...

Page 670: ...IT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9...

Page 671: ...g write requests is 16 0x10 0xFF Setting reserved bit7 0 ar2r_max_pipeline Defines the maximum number of outstanding AXI read requests that can be issued by the DMA via the AR channel Bits Description...

Page 672: ...ET 31 30 29 28 27 26 25 24 BIT_NAME address 31 24 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME address 23 16 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0...

Page 673: ...29 28 27 26 25 24 BIT_NAME address 63 56 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME address 55 48 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_...

Page 674: ...4 NUMERIC_TYPE OTHER BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME address 31 24 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME address 23 16 ACCESS_TYPE R...

Page 675: ...BIT_NAME Reserved filter_byte_mask 5 0 ACCESS_TYPE R0 WX R W PROT_TYPE Wp INITIAL_VALUE 0x0 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved filter_type ACCESS_TYPE R0 WX R W PROT_TYPE Wp INI...

Page 676: ...bit selects whether this filter should be comparing the MAC source address or the MAC destination address of the received Ethernet frame When set to 0 the filter is a destination address filter When s...

Page 677: ...R W R0 WX PROT_TYPE Wp INITIAL_VALUE 0 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME match 15 8...

Page 678: ...PE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME ipg_stretch 15 8 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME ipg_stretch 7 0 ACCESS_TYPE R W...

Page 679: ...VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME match 15 8 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME match 7 0 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE...

Page 680: ...ALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME vector 7 0 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME vector_enable 7 0 ACCESS_TYPE R W PROT_TYPE Wp INITIA...

Page 681: ...ment Number 002 04852 Rev G bit7 0 vector_enable Priority vector enable If bit 17 of the Network Control register is written with a 1 then the priority enable vector of the PFC priority based pause fr...

Page 682: ...27 26 25 24 BIT_NAME address_mask 31 24 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME address_mask 23 16 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00...

Page 683: ...rved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME...

Page 684: ...C_TYPE OTHER BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME address 31 24 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME address 23 16 ACCESS_TYPE R W PROT_TY...

Page 685: ...C_TYPE OTHER BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME address 31 24 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME address 23 16 ACCESS_TYPE R W PROT_TY...

Page 686: ...ved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME Reserved...

Page 687: ...value stored in bit 29 of this register When bit 2 is set the AXI address bit 30 used for accessing the receive data buffers will be forced to the value stored in bit 30 of this register When bit 3 i...

Page 688: ...YPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved comparison_value 21 16 ACCESS_TYPE R0 WX R W PROT_TYPE Wp INITIAL_VALUE 0x0 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAM...

Page 689: ...26 25 24 BIT_NAME comparison_value 31 24 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME comparison_value 23 16 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE...

Page 690: ...AME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 B...

Page 691: ...served ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME timer_seconds 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NA...

Page 692: ...erved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME timer_seconds 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAM...

Page 693: ...eserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME timer_seconds 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_N...

Page 694: ...served ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME timer_seconds 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NA...

Page 695: ...roduct specification BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME module_identification_number 7 0 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE product specification BIT_OFFSET 15 14 13 12 11 10 9 8 BIT...

Page 696: ...29 28 27 26 25 24 BIT_NAME count 31 24 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFF...

Page 697: ...rved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME...

Page 698: ...t 31 24 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_N...

Page 699: ...ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME cou...

Page 700: ...ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME cou...

Page 701: ...16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME count 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0...

Page 702: ...count 31 24 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 B...

Page 703: ...count 31 24 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 B...

Page 704: ...count 31 24 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8...

Page 705: ...count 31 24 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8...

Page 706: ...count 31 24 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8...

Page 707: ...E count 31 24 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8...

Page 708: ...AME count 31 24 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9...

Page 709: ...T 15 14 13 12 11 10 9 8 BIT_NAME count 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME count 7 0 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 bit31 0 coun...

Page 710: ...LUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved count 9 8 ACCESS_TYPE R0 WX R WX PROT...

Page 711: ...PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved count 17 16 ACCESS_TYPE R0 WX R WX PROT_TYPE Wp INITIAL_VALUE 0x00 0x0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME c...

Page 712: ...AL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved count 17 16 ACCESS_TYPE R0 WX R WX PROT_TYPE Wp INITIAL_VALUE 0x00 0x0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME count 15 8 ACCESS_TY...

Page 713: ...TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved cou...

Page 714: ...23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved count 9 8 ACCESS_TYPE R0 WX R WX PROT_TYPE Wp INITIAL_VA...

Page 715: ...19 18 17 16 BIT_NAME Reserved count 17 16 ACCESS_TYPE R0 WX R WX PROT_TYPE Wp INITIAL_VALUE 0x00 0x0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME count 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0...

Page 716: ...2 11 10 9 8 BIT_NAME Reserved count 9 8 ACCESS_TYPE R0 WX R WX PROT_TYPE Wp INITIAL_VALUE 0x00 0x0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME count 7 0 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 bit31...

Page 717: ...31 24 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NA...

Page 718: ...p INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME count 47 40 ACCESS_TYPE R WX PROT_...

Page 719: ...R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME count 15 8 ACCES...

Page 720: ...OT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME count 15 8 ACCESS_TYPE...

Page 721: ...OT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME count 15 8 ACCESS_TYPE...

Page 722: ...24 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11...

Page 723: ...OT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME count 15 8 ACCESS_TYPE...

Page 724: ...OT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME count 15 8 ACCESS_TYPE...

Page 725: ...ROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME count 15 8 ACCESS_TYPE...

Page 726: ...ROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME count 15 8 ACCESS_TYPE...

Page 727: ...ROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME count 15 8 ACCESS_TYPE...

Page 728: ...PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME count 15 8 ACCESS_TYP...

Page 729: ...17 16 BIT_NAME count 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME count 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2...

Page 730: ...Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved count 9 8 ACCESS_TYPE R...

Page 731: ...Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved count 9 8 ACCESS_TYPE R0 WX R WX PROT_TYPE Wp INITIAL_VALUE 0x00 0x0 BIT_OFFSET 7 6 5 4 3...

Page 732: ...erved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved count 9 8 ACCESS_TYPE R0 WX R WX PROT_TYPE Wp INITIAL_VALUE 0x00 0x0 BIT_OFFSET 7 6 5 4 3 2 1...

Page 733: ...WX PROT_TYPE Wp INITIAL_VALUE 0x00 0x0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME count 7 0 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 bit31 10 Reserved Always read 0 Writing has no effect bit9 0 count...

Page 734: ...WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved count 9 8 ACCESS_TYPE R0 WX R WX PROT_TYPE Wp INITIAL_VALUE 0x00 0x0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME count 7...

Page 735: ...T_NAME Reserved count 9 8 ACCESS_TYPE R0 WX R WX PROT_TYPE Wp INITIAL_VALUE 0x00 0x0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME count 7 0 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 bit31 10 Reserved Al...

Page 736: ...AME Reserved count 9 8 ACCESS_TYPE R0 WX R WX PROT_TYPE Wp INITIAL_VALUE 0x00 0x0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME count 7 0 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 bit31 10 Reserved Alway...

Page 737: ...7 16 ACCESS_TYPE R0 WX R WX PROT_TYPE Wp INITIAL_VALUE 0x00 0x0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME count 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAM...

Page 738: ...YPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved count 9 8 ACCESS_TYP...

Page 739: ...ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME count 7 0 AC...

Page 740: ...d ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME count 7 0 A...

Page 741: ...d ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME count 7 0 A...

Page 742: ..._NAME count 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME count 7 0 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 bit31 16 Reserved Always read 0 Writing...

Page 743: ...APTER 21 Ethernet MAC 742 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G action to flush a packet from the head of the PBUF queue is pulsed and the Ethernet MAC DMA is not currently bu...

Page 744: ...BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME count 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE...

Page 745: ...15 8 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME timer 7 0 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 bit31 16 Reserved Always read 0 Writing has no effect...

Page 746: ...16 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME timer 15 8 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME timer 7 0 AC...

Page 747: ...Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME timer 15 8 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME timer 7 0 ACCESS_TYPE R W PROT_TYPE Wp IN...

Page 748: ...9 18 17 16 BIT_NAME increment_value 23 16 ACCESS_TYPE R0 W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME increment_value 15 8 ACCESS_TYPE R0 W PROT_TYPE Wp INITIAL_VALUE 0x...

Page 749: ...21 20 19 18 17 16 BIT_NAME num_incs 7 0 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME alt_count 7 0 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFS...

Page 750: ...et MAC S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 749 bit7 0 count Count of nanoseconds A count of nanoseconds by which the IEEE 1588 Timer Nanoseconds register will be incremented...

Page 751: ...22 21 20 19 18 17 16 BIT_NAME timer 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME timer 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OF...

Page 752: ...7 16 BIT_NAME timer 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME timer 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2...

Page 753: ...22 21 20 19 18 17 16 BIT_NAME timer 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME timer 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OF...

Page 754: ...16 BIT_NAME timer 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME timer 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2 1...

Page 755: ...3 22 21 20 19 18 17 16 BIT_NAME timer 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME timer 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_O...

Page 756: ...17 16 BIT_NAME timer 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME timer 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2...

Page 757: ...23 22 21 20 19 18 17 16 BIT_NAME timer 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME timer 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_...

Page 758: ...7 16 BIT_NAME timer 23 16 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME timer 15 8 ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 7 6 5 4 3 2...

Page 759: ..._TYPE Wp INITIAL_VALUE 0xFF BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME quantum_p3 7 0 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0xFF BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME quantum_p2 15 8 ACCESS_...

Page 760: ...YPE Wp INITIAL_VALUE 0xFF BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME quantum_p5 7 0 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0xFF BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME quantum_p4 15 8 ACCESS_TY...

Page 761: ...YPE Wp INITIAL_VALUE 0xFF BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME quantum_p7 7 0 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0xFF BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME quantum_p6 15 8 ACCESS_TY...

Page 762: ...R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME count 15 8 ACCESS...

Page 763: ...PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME lpi_time 23 16 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME lpi_time 15 8 ACCES...

Page 764: ...PE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME count 15 8 ACC...

Page 765: ...TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME lpi_time 23 16 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME lpi_time 15 8 ACCESS_TYP...

Page 766: ..._add_filters ACCESS_TYPE R0 WX R WX PROT_TYPE Wp INITIAL_VALUE 0x0 0x04 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11...

Page 767: ...p INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved tx_base2_fifo_size 3 0 ACCESS_TYPE R0 WX R WX PROT_TYPE Wp INITIAL_VALUE 0x0 0x0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME tx_...

Page 768: ...x_buffer_length_def 3 0 tx_pbuf_siz e_def rx_pbuf_size_def endian_swa p_def 1 ACCESS_TYPE R WX R WX R WX R WX PROT_TYPE Wp INITIAL_VALUE 0x0 1 0x3 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME endian_sw...

Page 769: ...ndian_swap_def Writing has no effect bit14 12 mdc_clock_div Takes the value of gem_mdc_clock_div Writing has no effect bit11 10 dma_bus_width_def Takes the value of gem_dma_bus_width_def Writing has n...

Page 770: ...SS_TYPE R WX R WX R WX R WX R WX PROT_TYPE Wp INITIAL_VALUE product specification BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME dma_priorit y_queue15 dma_priorit y_queue14 dma_priorit y_queue13 dma_priori...

Page 771: ...ct bit14 dma_priority_queue14 Takes the value of gem_ dma_priority_queue14 Writing has no effect bit13 dma_priority_queue13 Takes the value of gem_ dma_priority_queue13 Writing has no effect bit12 dma...

Page 772: ..._queue4 Writing has no effect bit3 dma_priority_queue3 Takes the value of gem_ dma_priority_queue3 Writing has no effect bit2 dma_priority_queue2 Takes the value of gem_ dma_priority_queue2 Writing ha...

Page 773: ...tx_pbuf_num_segments_q5 tx_pbuf_num_segments_q4 ACCESS_TYPE R WX R WX PROT_TYPE Wp INITIAL_VALUE 0x0 0x0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME tx_pbuf_num_segments_q3 tx_pbuf_num_segments_q2 ACCES...

Page 774: ...12 tx_pbuf_num_segments_q3 Takes the value of gem_ tx_pbuf_num_segments_q3 Writing has no effect bit11 8 tx_pbuf_num_segments_q2 Takes the value of gem_ tx_pbuf_num_segments_q2 Writing has no effect b...

Page 775: ...BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME num_type2_screeners ACCESS_TYPE R WX PROT_TYPE Wp INITIAL_VALUE 0x10 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME num_scr2_ethtype_regs ACCESS_TYPE R WX PROT_T...

Page 776: ...CHAPTER 21 Ethernet MAC S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 775 bit7 0 num_scr2_compare_regs Takes the value of gem_ num_scr2_compare_regs Writing has no effect...

Page 777: ...buf_num_segments_q13 tx_pbuf_num_segments_q12 ACCESS_TYPE R WX R WX PROT_TYPE Wp INITIAL_VALUE 0x0 0x0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME tx_pbuf_num_segments_q11 tx_pbuf_num_segments_q10 ACCES...

Page 778: ...2 tx_pbuf_num_segments_q11 Takes the value of gem_ tx_pbuf_num_segments_q11 Writing has no effect bit11 8 tx_pbuf_num_segments_q10 Takes the value of gem_ tx_pbuf_num_segments_q10 Writing has no effec...

Page 779: ...1 20 19 18 17 16 BIT_NAME rx_pbuf_data axi_access_pipeline_bits ACCESS_TYPE R WX R WX PROT_TYPE Wp INITIAL_VALUE 0x2 0x4 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME axi_tx_desc_rd_buff_bits axi_rx_desc_...

Page 780: ...axi_tx_desc_rd_buff_bits Takes the value of gem_ axi_tx_desc_rd_buff_bits Writing has no effect bit11 8 axi_rx_desc_rd_buff_bits Takes the value of gem_ axi_rx_desc_rd_buff_bits Writing has no effect...

Page 781: ...PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved resp_not_o k r...

Page 782: ...rror Transmit frame corruption due to AMBA AXI error Bit Description 0 Interrupt de asserted 1 Interrupt asserted Set if an error occurs whilst midway through reading transmit frame from system memory...

Page 783: ...turns the location of the descriptor currently being accessed Since the DMA handles two frames at once this may not necessarily be pointing to the current frame being transmitted In terms of AMBA AXI...

Page 784: ...MAC S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 783 bit31 2 dma_tx_q_ptr Transmit buffer queue base address Start address of transmit buffer queue bit1 0 Reserved Always read 0 Wri...

Page 785: ...turns the location of the descriptor currently being accessed Since the DMA handles two frames at once this may not necessarily be pointing to the current frame being transmitted In terms of AMBA AXI...

Page 786: ...MAC S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 785 bit31 2 dma_tx_q_ptr Transmit buffer queue base address Start address of transmit buffer queue bit1 0 Reserved Always read 0 Wri...

Page 787: ...turns the location of the descriptor currently being accessed Since the DMA handles two frames at once this may not necessarily be pointing to the current frame being transmitted In terms of AMBA AXI...

Page 788: ...MAC S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 787 bit31 2 dma_tx_q_ptr Transmit buffer queue base address Start address of transmit buffer queue bit1 0 Reserved Always read 0 Wri...

Page 789: ...new frames are received Software should instead work its way through the buffer descriptor queue checking the used bits In terms of AMBA AXI operation the receive descriptors are read from memory usin...

Page 790: ...t MAC S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 789 bit31 2 dma_rx_q_ptr Receive buffer queue base address Start address of receive buffer queue bit1 0 Reserved Always read 0 Writ...

Page 791: ...new frames are received Software should instead work its way through the buffer descriptor queue checking the used bits In terms of AMBA AXI operation the receive descriptors are read from memory usin...

Page 792: ...t MAC S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 791 bit31 2 dma_rx_q_ptr Receive buffer queue base address Start address of receive buffer queue bit1 0 Reserved Always read 0 Writ...

Page 793: ...new frames are received Software should instead work its way through the buffer descriptor queue checking the used bits In terms of AMBA AXI operation the receive descriptors are read from memory usin...

Page 794: ...t MAC S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 793 bit31 2 dma_rx_q_ptr Receive buffer queue base address Start address of receive buffer queue bit1 0 Reserved Always read 0 Writ...

Page 795: ...23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OF...

Page 796: ...Manual Document Number 002 04852 Rev G 795 Bits Description 0x02 128 Byte 2 64 Byte 0x18 1536 Byte 24 64 Byte one maximum length frame buffer 0xA0 10240 Byte 160 64 Byte one jumbo frame buffer 0xF0 15...

Page 797: ...ueue would be calculated as 017D7840h 2 Note Credit Based Shaping shall be disabled prior to updating the idleSlope values REGISTER_NAME ETHERNETn_cbs_control OFFSET 0x4BC ACCESS_SIZE W MULTIPLE NUMER...

Page 798: ...it1 cbs_enable_queue_b Enable Credit Based Shaping on 2nd Highest Priority Queue Bit Description 0 CBS on Queue B disabled 1 CBS on Queue B enabled bit0 cbs_enable_queue_a Enable Credit Based Shaping...

Page 799: ...eslope_a 31 24 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME idleslope_a 23 16 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 1...

Page 800: ...ope_b 31 24 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME idleslope_b 23 16 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9...

Page 801: ...HER BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME msb_buff_q_base_addr 31 24 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME msb_buff_q_base_addr 23 16 ACCESS...

Page 802: ...23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OF...

Page 803: ...CHAPTER 21 Ethernet MAC 802 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G bit3 0 Reserved Always read 0 Writing has no effect...

Page 804: ...23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFF...

Page 805: ...CHAPTER 21 Ethernet MAC 804 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G bit3 0 Reserved Always read 0 Writing has no effect...

Page 806: ...oth UDP and DS TC matching can be enabled simultaneously or individually If a match is successful then the queue value programmed in bits 3 0 is allocated to the frame REGISTER_NAME ETHERNETn_screenin...

Page 807: ..._enable DS TC enable Bit Description 0 Disable 1 Enable bit27 12 udp_port_match UDP port match UDP Destination Port of the received UDP frame is matched against this value bit11 4 dstc_match DS TC mat...

Page 808: ...ed field Compare A 4 An enabled field Compare B 5 An enabled field Compare C REGISTER_NAME ETHERNETn_screening_type_2_register_i OFFSET 0x540 i 0x4 ACCESS_SIZE W MULTIPLE 0 15 NUMERIC_TYPE OTHER BIT_O...

Page 809: ...compare_b Compare B Index to screener type 2 Compare register bit18 compare_a_enable Compare A enable Bit Description 0 Disable 1 Enable bit17 13 compare_a Compare A Index to screener type 2 Compare...

Page 810: ...T_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved enable_res p_not_ok_in terrupt enable_rec eive_o...

Page 811: ..._frame_corruption_due_to_amba_error_interrupt Enable Transmit frame corruption due to AMBA AXI error interrupt Writing 1 enables Transmit frame corruption due to AMBA AXI error interrupt bit5 enable_r...

Page 812: ...0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved disable_res p_not_ok_in terrupt disable_r...

Page 813: ...rupt bit6 disable_transmit_frame_corruption_due_to_amba_error_interrupt Disable Transmit frame corruption due to AMBA AXI error interrupt Writing 1 disables Transmit frame corruption due to AMBA AXI e...

Page 814: ...be set or cleared regardless of the state of the mask register REGISTER_NAME ETHERNETn_int_mask_qi OFFSET 0x640 i 1 0x4 ACCESS_SIZE W MULTIPLE 1 3 NUMERIC_TYPE OTHER BIT_OFFSET 31 30 29 28 27 26 25 24...

Page 815: ...mask Transmit complete interrupt mask A write to this register directly affects the state of the corresponding bit in the Interrupt Status Queue i register causing an interrupt to be generated if a 1...

Page 816: ...register causing an interrupt to be generated if a 1 is written Bit Description 0 Interrupt disabled 1 Interrupt enabled bit1 receive_complete_interrupt_mask Receive complete interrupt mask A write to...

Page 817: ...THER BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_...

Page 818: ...UE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME compare_value 7 0 ACCESS_TYPE R W PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME mask_value 15 8 ACCESS_TYPE R W PROT_TYP...

Page 819: ..._TYPE OTHER BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0x00 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp I...

Page 820: ...compare_offset 1 0 Compare offset Compare byte offset Bits Description 00 Offset from beginning of frame 01 Offset from byte after EtherType 10 Offset from byte following end of IP header 11 Offset fr...

Page 821: ...or 11 When only the byte matching is designated screener type2 potentially produces a match for non IP TCP frames since it doesn t check the type of frames To specify the type of frames to match the e...

Page 822: ...80 C2 00 00 0E is used by only the Pdelay Request frames and Pdelay Response frames And the SYNC frames use the destination address 01 1B 19 00 00 00 In the IEEE Std 802 1AS compliant system The fram...

Page 823: ...Number 002 04852 Rev G CHAPTER 22 Media Local Bus Interface MediaLB This chapter explains the functions and operations of the MediaLB 1 Overview 2 Configuration and Block Diagram 3 Operation of the M...

Page 824: ...f the MediaLB Implements the Physical and Link Layer requirements outlined in MediaLB Specification rev 3 0 Transmits commands and data when functioning as the transmitting device Receives data and tr...

Page 825: ...en the MediaLB and system memory via the AHB bus Current buffer The data area on the AHB bus that is read written in DMA mode Current buffer address Indicates the address area that is output next on t...

Page 826: ...iagram of MediaLB Figure 2 1 MediaLB Block Diagram MediaLB Channel Arbiter MediaLB Link Logic MediaLB Clocks Power and Reset MediaLB Core MediaLB Channel Buffer Logic MediaLB Configuration Logic AHB S...

Page 827: ...asters higher PERI4 clock frequencies are recommended MediaLB IO Mode The IO mode dictates a particular method used for transferring data between the local channel buffer and the system memory For cha...

Page 828: ...Channel n Buffer Configuration Register MLBn_LCBCRn For details on the Local channel buffer operation please contact SMSC Interrupts by MediaLB This section describes interrupts that MediaLB has Media...

Page 829: ...mit service request All channels enabled for transmitting MLBn_CECRn MASK 3 Writing 1 to STS 3 STS 8 Received packet aborted Async and control channels enabled for receiving MLBn_CECEn MASK 2 Writing...

Page 830: ...MediaLB lock SDML MLBn_SMCR SMML Writing 1 to SDML Detecting a MediaLB unlock SDMU MLBn_SMCR SMMU Writing 1 to SDMU Loop Back Mode To facilitate debugging of transmission paths MediaLB supports the l...

Page 831: ...ble in user mode PPU should be configured accordingly Steps in Programming the MediaLB Module After the system reset the software shall detect the Module ID number of MediaLB by reading the MLBn_MID r...

Page 832: ...nfiguration Register MLBn_SSCR MediaLBn System Data Configuration Register MLBn_SDCR MediaLBn System Mask Configuration Register MLBn_SMCR MediaLBn Version Control Configuration Register MLBn_VCCR Med...

Page 833: ...0024 MLBn_ABCR 00000000 00000000 00000000 00000000 0x00000028 MLBn_CBCR 00000000 00000000 00000000 00000000 0x0000002C MLBn_IBCR 00000000 00000000 00000000 00000000 0x00000030 MLBn_CICR 00000000 00000...

Page 834: ...0000000 00000000 0x00000084 MLBn_CSCR4 10000000 00000000 00000000 00000000 0x00000088 MLBn_CCBCR4 00000000 00000000 00000000 00000000 0x0000008C MLBn_CNBCR4 00000000 00000000 00000000 00000000 0x00000...

Page 835: ...0 00000000 0x000000E0 MLBn_CECR10 00000000 00000000 00000000 00000000 0x000000E4 MLBn_CSCR10 10000000 00000000 00000000 00000000 0x000000E8 MLBn_CCBCR10 00000000 00000000 00000000 00000000 0x000000EC...

Page 836: ...000 00000000 0x0000013C MLBn_CNBCR15 00000000 00000000 00000000 00000000 0x00000140 0x0000027C reserved XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX 0x00000280 MLBn_LCBCR0 00000000 01000000 00000000 00000000 0...

Page 837: ...BCR12 00000000 01000000 00000000 00000000 0x000002B4 MLBn_LCBCR13 00000000 01000000 00000000 00000000 0x000002B8 MLBn_LCBCR14 00000000 01000000 00000000 00000000 0x000002BC MLBn_LCBCR15 00000000 01000...

Page 838: ...FSET 31 30 29 28 27 26 25 24 BIT_NAME MDE LBM MCS 1 MCS 0 M5PS MLK MLE MHRE ACCESS_TYPE R W R W R W R W R W R WX R W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_...

Page 839: ...Loop back test mode 1 Enables Loop back test mode Note For more information on Loop BackTest mode please contact SMSC support bit29 28 MCS 1 0 MediaLB Clock Select Sets the MediaLB transfer rate This...

Page 840: ...Bit Description 0 Big Endian mode 1 Little Endian mode bit24 MHRE MediaLB Hardware Reset Enable This bit enables the hardware to automatically reset the MediaLB physical and link layer logic upon rece...

Page 841: ...vice Address The MediaLB Device Address MDA 8 1 sets a unique Device Address DA for the MediaLB Device The device address is a 16 bit address allocated to identify the MediaLB device The DA is used by...

Page 842: ...5 24 BIT_NAME read0 read0 read0 read0 read0 read0 read0 read0 ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT...

Page 843: ...L System Detects MediaLB Lock Bit Description 0 MediaLB lock not detected 1 MediaLB lock detected This bit is set to indicate that the MediaLB Device has locked to the MediaLB frame If not masked by t...

Page 844: ...ster MLBn_SMCR SMNL a system interrupt is generated on detection of the MOST_Lock command Write 1 to clear this bit Writing 0 has no effect Once set this bit holds until it is cleared by software bit0...

Page 845: ...23 22 21 20 19 18 17 16 BIT_NAME MSD 23 MSD 22 MSD 21 MSD 20 MSD 19 MSD 18 MSD 17 MSD 16 ACCESS_TYPE R WX R WX R WX R WX R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13...

Page 846: ...read0 read0 read0 ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME read0 read0 read0 read0 read0 read0 re...

Page 847: ...be masked when the subcommand of the system command MlbSubCmd 0xE6 is received The receipt of a subcommand of the system command MlbSubCmd 0xE6 is indicated by MLBn_SSCR SDSC Bit Description 0 Interr...

Page 848: ...on 0 Interrupt due to the receipt of the MOST_Lock 0xE0 system command is not masked 1 Interrupt due to the receipt of the MOST_Lock 0xE0 system command is masked bit0 SMR System Masks Reset Sets whet...

Page 849: ...X R WX R WX R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME UMI 7 UMI 6 UMI 5 UMI 4 UMI 3 UMI 2 UMI 1 UMI 0 ACCESS_TYPE R WX R WX R WX R WX R WX...

Page 850: ...e MediaLB module OS62400 on this device This value is hard coded by the vendor Note For OS62400 version code information refer to the device datasheet bit7 0 MMI 7 0 MediaLB Minor Revision Code MediaL...

Page 851: ...NAME SRBA 7 SRBA 6 SRBA 5 SRBA 4 SRBA 3 SRBA 2 SRBA 1 SRBA 0 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME STBA 15 STBA...

Page 852: ...e Address for DMA mode These bits allow the system software to define the base address STBA 31 16 for synchronous transmit system memory buffers in DMA mode This base address is shared by all synchron...

Page 853: ...E ARBA 7 ARBA 6 ARBA 5 ARBA 4 ARBA 3 ARBA 2 ARBA 1 ARBA 0 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME ATBA 15 ATBA 14...

Page 854: ...ess for DMA mode These bits allow the system software to define the base address ATBA 31 16 for asynchronous transmit system memory buffers in DMA mode This base address is shared by all asynchronous...

Page 855: ...A 7 CRBA 6 CRBA 5 CRBA 4 CRBA 3 CRBA 2 CRBA 1 CRBA 0 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME CTBA 15 CTBA 14 CTBA...

Page 856: ...ddress for DMA mode These bits allow the system software to define the base address CTBA 31 16 for control transmit system memory buffers in DMA mode This base address is shared by all control transmi...

Page 857: ...RBA 7 IRBA 6 IRBA 5 IRBA 4 IRBA 3 IRBA 2 IRBA 1 IRBA 0 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME ITBA 15 ITBA 14 ITB...

Page 858: ...ress for DMA mode These bits allow the system software to define the base address ITBA 31 16 for isochronous transmit system memory buffers in DMA mode This base address is shared by all isochronous t...

Page 859: ...INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME read0 read0 read0 read0 read0 read0 read0 read0 ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX PROT_TYPE INITIAL...

Page 860: ...te Writing to the MLBn_CICR register has no effect To clear a particular bit in MLBn_CICR software must clear all of the unmasked status bits in the corresponding MLBn_CSCRn register For example if ML...

Page 861: ...T_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME MAXTRANS 7 MAXTRANS 6 MAXTRANS 5 MAXTRANS 4 MAXTRANS 3 MAXTRANS 2 MAXTRANS 1 MAXTRANS 0 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE INITIAL_VALUE 0...

Page 862: ...ZE B H W MULTIPLE 0 15 NUMERIC_TYPE OTHER MediaLB Channel Entry Configuration Register MLBn_CECR0 MLBn_CECR15 BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME CE TR CT 1 CT 0 FCE MDS 1 MDS 0 read0 ACCESS_T...

Page 863: ...nse Bit Description 0 Generation of ReceiverBusy 0x10 response prohibited 1 Generation of ReceiverBusy 0x10 response allowed For Asynchronous and control channel this bit PCE sets whether the receptio...

Page 864: ...depending on DMA mode or IO mode and sets the mask for channel interrupts The status bit targeted for masking is CSCRn STS 3 For DMA mode it masks the buffer start interrupt For IO mode it masks the...

Page 865: ...s the number of physical channels that match with the channel address CECRn CA 8 1 among the synchronous channels contained in one frame For Asynchronous Control channel IPL 7 5 These bits are not use...

Page 866: ...15 NUMERIC_TYPE OTHER MediaLB Channel Status Configuration Register MLBn_CSCR0 MLBn_CSCR15 BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME BM BF read0 read0 read0 read0 read0 read0 ACCESS_TYPE R WX R WX...

Page 867: ...te CCBCRn BCA 3 11 Final valid byte CCBCRn BCA 2 bit17 GB Generate Break This bit has different interpretation depending on the channel configuration For Synchronous channel this bit is not used For I...

Page 868: ...ding on DMA mode or IO mode In DMA mode this is the Previous Buffer Done bit When set this bit indicates the last quadlet of the Previous Buffer has been successfully transmitted or received The setti...

Page 869: ...a receive channel has detected an aborted packet Received packets are aborted if the receiver generates a break response ReceiverBreak 0x70 or detects a transmitter packet break command ControlBreak 0...

Page 870: ...uadlets in the local channel buffer is less than or equal to MLBn_LCBCRn TH 6 0 The setting of this bit generates a maskable channel interrupt to the system software This bit is valid for all channel...

Page 871: ...etected an RxStatus of ReceiverProtocolError 0x72 a receive channel has detected an invalid command for a given channel type or an additional ControlStart 0x30 or AsyncStart 0x20 command has been rece...

Page 872: ...27 26 25 24 BIT_NAME BCA 15 BCA 14 BCA 13 BCA 12 BCA 11 BCA 10 BCA 9 BCA 8 ACCESS_TYPE R WX R WX R WX R WX R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 1...

Page 873: ...BFA 15 2 bits are loaded from MLBn_CNBCRn BEA 15 2 when the Next Buffer is read for processing This Current Buffer address pointer except when associated with isochronous channels should always be qu...

Page 874: ...iguration Register MLBn_CNBCR0 MLBn_CNBCR15 BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME BSA 15 BSA 14 BSA 13 BSA 12 BSA 11 BSA 10 BSA 9 BSA 8 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE INIT...

Page 875: ...t15 0 BEA 15 0 Buffer End Address bits This bit field has different interpretations for DMA mode and IO mode In DMA mode the BEA field defines a 16 bit address pointer which identifies the lower half...

Page 876: ...ET 0 i 4 ACCESS_SIZE B H W MULTIPLE 0 15 NUMERIC_TYPE OTHER MediaLB Local Channel Buffer Configuration Register MLBn_LCBCR0 MLBn_LCBCR15 BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME read0 read0 read0 T...

Page 877: ...4 quadlets 0x7F Threshold 254 quadlets bit21 19 read0 bit18 13 BD 5 0 Buffer Depth BD 5 0 sets the depth of the local channel buffer The depth is set in units of 4 quadlets BD 5 0 Description 0x00 De...

Page 878: ...MID 21 MID 20 MID 19 MID 18 MID 17 MID 16 ACCESS_TYPE R WX R WX R WX R WX R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME MID 15 MID 14 MID 13 MI...

Page 879: ...nual Document Number 002 04852 Rev G CHAPTER 23 Stereo Audio DAC This chapter presents the Stereo Audio Digital to Analog Converter DAC 1 Overview 2 Configuration and Block Diagram 3 Operation 4 Regis...

Page 880: ...alog DAC and features a software power down function for lower power consumption The audio data format of the digital interface is a 32 bit word the upper lower 16 bits are used as the data for the le...

Page 881: ...d The sequence for powering up the analog DAC is as follows 1 Configure the OSR and DACCLK bit of the DAOSR register 2 Write a 1 into the INIT bit and DAE bit of the DACR register This will release th...

Page 882: ...the FIFO while the down counter is zero Note The block size configured in the DMA must match DACTRL_FEST 1 3 3 Output Data Values of the Analog DAC The data output pins of the analog DAC will be set t...

Page 883: ...te into the DCR register Write into the DOSR register Write into the DCR register Write into the DCR register 3 6 Interrupt The Stereo Audio DAC module interrupts are controlled by three registers the...

Page 884: ...size 8 16 32bit only Width of address 10bit The following accesses cause the slave error response 1 When the access destination is an address that does not exist in the memory map 2 The write access w...

Page 885: ...frequency Table 5 System Clock and over Sampling Ratio Sampling frequency fs kHz pin setting OSR system clock frequency OSR 1 0 8 11 025 12 11 512 512fs 16 22 05 24 10 256 256fs 32 44 1 48 01 128 256...

Page 886: ...448 MHz 1 10 112 896 MHz 1 16 90 3168 MHz 1 16 180 6336 MHz 24kHz 6 144MHz 1 1 6 144 MHz 12 288MHz 1 1 12 288 MHz 1 2 12 288 MHz 1 2 24 576 MHz 1 8 49 152 MHz 1 8 98 304 MHz 1 10 61 44 MHz 1 10 122 8...

Page 887: ...dio DAC mounts the method of connection by Bridge tied load BTL When BTL is used output L and R of Audio DAC become the signal outputs with the phase difference of 180 It is necessary to reverse the p...

Page 888: ...Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved Reserved...

Page 889: ...lock CLKDACI 8 001 Divide by 10 Conversion clock CLKDACI 10 010 Divide by 16 Conversion clock CLKDACI 16 011 Divide by 2 Conversion clock CLKDACI 2 100 Divide by 1 Conversion clock CLKDACI other Not a...

Page 890: ...0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL...

Page 891: ...alue to the analog DAC default 1 The digital interface logic will be initialized and output a 00000000h value to the analog DAC bit7 1 Reserved This bit is reserved Always write 0 to this bit The read...

Page 892: ...ed Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved Reserved Reserved Reserve...

Page 893: ...002 04852 Rev G Note The write access to the DAOSR DACR register uses the asynchronous circuit from CLKPI to CLKDA DABUSY field indicates that the write access to DAOSR DACR register has not been comp...

Page 894: ...19 18 17 16 BIT_NAME Reserved Reserved Reserved FEST4 FEST3 FEST2 FEST1 FEST0 ACCESS_TYPE R0 W0 R0 W0 R0 W0 R W R W R W R W R W PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10...

Page 895: ...erated when the number of empty FIFO buffer entries exceeds this value If this field is set to a value greater than 23 DAC_DMA_REQ and DAC_DATA_REQ_IRQ are never generated These bits must not be chang...

Page 896: ...eserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Re...

Page 897: ...CHAPTER 23 Stereo Audio DAC 896 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G Note The write access to this register is effective at DACR_INIT 1...

Page 898: ...IAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W...

Page 899: ...Run Error Explanation of UDRN Bit Description 0 The FIFO under run error interrupt is disabled default 1 The FIFO under run error interrupt is enabled bit1 OVFL FIFO Overflow Error Explanation of OVF...

Page 900: ...R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserve...

Page 901: ...ut the FIFO buffer is empty bit1 OVFL FIFO Overflow Error Explanation of OVFL Bit Description 0 No error 1 A FIFO buffer overflow has occurred i e there was a write access to the FIFO buffer when ther...

Page 902: ...0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE W...

Page 903: ...to this bit clears the FIFO under run error interrupt This bit is always read as 0 bit1 OVFL FIFO Overflow Error Explanation of OVFL Bit Description 0 Leave the FIFO overflow error interrupt unchange...

Page 904: ...LUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT...

Page 905: ...CL The upper 16bits Left DATA Polarity conversion Explanation of PCL Bit Description 0 No influence 1 LDATA Polarity conversion bit0 PCR The lower 16bits Right DATA polarity conversion Explanation of...

Page 906: ...NAME DADR15 DADR14 DADR13 DADR12 DADR11 DADR10 DADR9 DADR8 ACCESS_TYPE RX W RX W RX W RX W RX W RX W RX W RX W PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME DADR7 DADR...

Page 907: ...04852 Rev G CHAPTER 24 Inter IC Sound I2S This chapter explains the functions and operations of the serial audio interface that is the Inter IC Sound I2S 1 Overview 2 Configuration and Block Diagram 3...

Page 908: ...eption FIFO and internal system memory can be performed by DMA interrupt and polling Features of I2S I2S interface has the following features Programmable master slave operations Support of transmissi...

Page 909: ...gured in master mode and act as input line in slave mode DMA controller is used for DMA access Clocking of I2S The supply clock of I2S can be internal or external ECLK source This clock is then pre sc...

Page 910: ...sub frame is determined by I2Sn_MCR0REG S0CHN Up to 32 channels can be set Each channel bit length word length is determined by I2Sn_MCR0REG S0WDL Sub frame channel starts from 0th Each channel is se...

Page 911: ...nding bit of I2Sn_MCR1REG register and corresponding bit of I2Sn_MCR2REG register for sub frame 1 Transmission reception of data is not performed to invalid channel Dummy bit can be inserted behind su...

Page 912: ...or 1 by the register setting Burst mode I2Sn_CNTREG FRUN 0 If transmission FIFO is not empty I2Sn_OPRREG START bit is 1 and I2Sn_OPRREG TXENB bit is 1 frame synchronous signal is output After complet...

Page 913: ...data is output to serial bus I2Sn_OPRREG TXENB 0 When 0 is written to I2Sn_OPRREG TXENB transmission FIFO becomes empty and data present in the transmission FIFO at the time 0 was written to I2Sn_OPRR...

Page 914: ...e of stop frame is not imported from serial bus even though reception FIFO is empty To maintain I2Sn_OPRREG START bit to 1 When 0 is written to I2Sn_OPRREG RXENB reception FIFO becomes empty Although...

Page 915: ...START 1 I2Sn_OPRREG TXENB 0 and I2Sn_OPRREG RXENB 1 The same operation as reception only mode I2Sn_OPRREG START 1 I2Sn_OPRREG TXENB 1 and I2Sn_OPRREG RXENB 1 Frame synchronous signal is output from t...

Page 916: ...I2Sn_OPRREG RXENB reception FIFO becomes empty and frame reception operation stops To make I2Sn_OPRREG START bit 0 When 0 is written to I2Sn_OPRREG START transmission reception FIFO becomes empty The...

Page 917: ...eption FIFO occurs while it is full I2Sn_STATUS RXOVR is set to 1 When reading from transmission FIFO occurs while it is empty empty frame bit is output For the setting conditions of I2Sn_STATUS TXUDR...

Page 918: ...the word length is prohibited Notes AB0 AB1 AB2 AB3 AH0 AH1 and AW on the above chart indicate byte 0 byte 1 byte 2 byte 3 half word 0 half word 1 and word at write accessing to I2Sn_TXFDAT0 to 15 on...

Page 919: ...ws Word length 8 or less byte 0 9 16 half word 0 17 32 all words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 920: ...w When I2Sn_CNTREG TXDIS 0 and I2Sn_CNTREG RXDIS 0 the mode is set to simultaneous transfer mode which operates with 66 word x 32 bit transmission and reception FIFOs FIFO To transmssion pin From rece...

Page 921: ...XDIS 0 and I2Sn_CNTREG RXDIS 1 the mode is set to transmission only mode which operates with a 132 word x 32 bit transmission FIFO and reception is not performed W R R W SWITCH FIFO To transmssion pin...

Page 922: ...XDIS 1 and I2Sn_CNTREG RXDIS 0 the mode is set to reception only mode which operates with a 132 word x 32 bit reception FIFO and transmission is not performed W R R W SWITCH FIFO From reception pin To...

Page 923: ...CR0REG S0WDL and I2Sn_MCR0REG S1WDL remaining bits in the channel become I2Sn_CNTREG MSKB Setting the channel length to shorter than the word length is prohibited Pulse width of one channel I2Sn_CNTRE...

Page 924: ...Register I2Sn_SRST Interrupt Control Register I2Sn_INTCNT Status Register I2Sn_STATUS DMA Activate Register I2Sn_DMAACT Debug Register I2Sn_DEBUG Module ID Register I2Sn_MIDREG Memory Layout of I2S Re...

Page 925: ...0000 00000000 00000000 00000000 B H W 0x00000048 I2Sn_TXFDAT2 00000000 00000000 00000000 00000000 B H W 0x0000004C I2Sn_TXFDAT3 00000000 00000000 00000000 00000000 B H W 0x00000050 I2Sn_TXFDAT4 000000...

Page 926: ...0000000 B H W 0x0000008C I2Sn_MCR2REG 00000000 00000000 00000000 00000000 B H W 0x00000090 I2Sn_OPRREG 00000000 00000000 00000000 00000000 B H W 0x00000094 I2Sn_SRST 00000000 00000000 00000000 0000000...

Page 927: ...R WX R WX R WX R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME RXDATA 15 RXDATA 14 RXDATA 13 RXDATA 12 RXDATA 11 RXDATA 10 RXDATA 9 RXDATA 8 ACCE...

Page 928: ...ess to this register the Rx FIFO read pointer is incremented provided that the read cycle was initiated by the AHB master other than the Debug Access Port DAP controller If the DAP controller reads th...

Page 929: ...17 16 BIT_NAME TXDATA 23 TXDATA 22 TXDATA 21 TXDATA 20 TXDATA 19 TXDATA 18 TXDATA 17 TXDATA 16 ACCESS_TYPE R0 W R0 W R0 W R0 W R0 W R0 W R0 W R0 W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 1...

Page 930: ...W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME OVHD 7 OVHD 6 OVHD 5 OVHD 4 OVHD 3 OVHD 2 OVHD 1 OVHD 0 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE...

Page 931: ...e The value set to OVHD becomes the number of insertion bits The following expressions are formed for OVHD and frame synchronous signal cycle 1 sub frame construction OVHD Frame synchronous signal cyc...

Page 932: ...FIFO word is handled as 2 half words at serial bus with dividing 16 bits each to low order and high order They are transferred by serial bus in order of low order high order low order and high order...

Page 933: ...Word bit s shift order is set Bit Description 0 Shift starts from MSB of the word 1 Shift starts from LSB of the word bit6 TXDIS Transmitter Disable Transmitting function is enabled or disabled Bit De...

Page 934: ...of frame data bit1 FSLN Frame Sync Pulse Width Pulse width of WS is specified Bit Description 0 Pulse width is 1 cycle SCK long 1 bit 1 Pulse width is 1 channel long 1 channel Pulse width of one chan...

Page 935: ..._TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME S1CHL 2 S1CHL 1 S1CHL 0 S1WDL 4 S1WDL 3 S1WDL 2 S1WDL 1 S1WDL 0 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE IN...

Page 936: ...e channel constructing sub frame 1 bit length of channel is set 7 to 32 bits of channel length are available but 1 to 6 bits are prohibited S1CHL needs to be set to channel length 1 Setting examples a...

Page 937: ...me construction I2Sn_CNTREG SBFN is 1 and is invalid in 1 sub frame construction I2Sn_CNTREG SBFN is 0 bit15 read0 bit14 10 S0CHN Sub Frame 0 Channel Numbers Number of channels of sub frame 0 is set u...

Page 938: ...length is 32 bits Channel length can be set to 32 bits or less regardless of I2Sn_CNTREG RHLL bit4 0 S0WDL Sub Frame 1 Word Length word length of the channel constructing sub frame 0 bit length of cha...

Page 939: ...W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME S0CH 15 S0CH 14 S0CH 13 S0CH 12 S0CH 11 S0CH 10 S0CH 9 S0CH 8 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_...

Page 940: ...0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME S1CH 15 S1CH 14 S1CH 13 S1CH 12 S1CH 11 S1CH 10 S1CH 9 S1CH 8 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_...

Page 941: ...ROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME read0 read0 read0 read0 read0 read0 read0 read0 ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX PROT_TYPE I...

Page 942: ...0 the data written to Transmission FIFO Data Registers from CPU or DMA is not written to transmission FIFO DMA transmit channel stops during DMA transfer 1 Transmit operation is enabled bit15 8 read0...

Page 943: ...15 14 13 12 11 10 9 8 BIT_NAME read0 read0 read0 read0 read0 read0 read0 read0 ACCESS_TYPE R0 W R0 W R0 W R0 W R0 W R0 W R0 W R0 W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 7 6 5 4 3 2 1 0 B...

Page 944: ...1 1 1 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME read0 read0 read0 read0 TFTH 3 TFTH 2 TFTH 1 TFTH 0 ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R W R W R W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFF...

Page 945: ...pt to CPU by I2Sn_STATUS TXUDR0 is masked bit26 TXOVM Tx FIFO Overflow Interrupt Mask This is transmission FIFO overflow interrupt mask bit It becomes 1 by software reset Bit Description 0 Interrupt t...

Page 946: ...rupt mask bit of reception FIFO overflow It becomes 1 by software reset Bit Description 0 Interrupt to CPU by I2Sn_STATUS RXOVR is not masked 1 Interrupt to CPU by I2Sn_STATUS RXOVR is masked bit18 EO...

Page 947: ...ets time out value of the internal reception completion timer Reception FIFO is not empty and number of its data is smaller than or equal to threshold value the timer always counts up Reception FIFO i...

Page 948: ...INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME TXNUM 7 TXNUM 6 TXNUM 5 TXNUM 4 TXNUM 3 TXNUM 2 TXNUM 1 TXNUM 0 ACCESS_TYPE R WX R WX R WX R WX R WX R WX R WX R WX PROT_TYPE I...

Page 949: ...the start of frame the value is set to 1 When TXUDR1 is 1 and I2Sn_INTCNT TXUD1M is 0 interrupt to the CPU occurs Writing 1 from CPU clears the value to 0 This bit becomes 0 by software reset Note Whe...

Page 950: ...n RXOVR is 1 and I2Sn_INTCNT RXOVM is 0 interrupt to CPU occurs Writing 1 from CPU clears the value to 0 This bit becomes 0 by software reset bit23 20 read0 bit19 EOPI Interrupt Flag for Rx Timer This...

Page 951: ...cess bit16 RXFI Rx FIFO Full When number of reception FIFO data becomes more than the threshold set in I2Sn_INTCNT RFTH this bit is set to 1 This bit is 1 and I2Sn_INTCNT interrupt to CPU occurs When...

Page 952: ...ALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME read0 read0 read0 read0 read0 read0 read0 TDMACT ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R W PROT_TYPE INITIAL_VALUE 0 0...

Page 953: ...et Bit Description 0 DMA transmission channel is disabled 1 DMA transmission channel is enabled Clearing TDMACT also clears write transmission request bit15 8 read0 bit7 1 read0 bit0 RDMACT Rx DMA Con...

Page 954: ..._TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME read0 read0 read0 read0 read0 read0 read0 read0 ACCESS_TYPE R0 W...

Page 955: ...04852 Rev G When DBGE is set to 1 and the processor is in debug state and I2S is working as a master then the serial interface is halted by stopping the activity on the SCK output The activity on the...

Page 956: ...21 MID 20 MID 19 MID 18 MID 17 MID 16 ACCESS_TYPE R WX R WX R WX R WX R WX R WX R WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME MID 15 MID 14 MID 13 MID 12...

Page 957: ...t Number 002 04852 Rev G CHAPTER 25 Programmable CRC This chapter explains the function and operation of the Programmable CRC 1 Overview 2 Configuration and Block Diagram 3 Operation of the Programmab...

Page 958: ...32 bit input data width Programmable polynomial value polynomial degree from 2 to 32 Programmable initial seed value Programmable final checksum XOR value Interrupt and DMA trigger capability Configur...

Page 959: ...ample for CRC calculation see Section 3 3 3 1 CRC Operation Flowcharts The flowcharts Figure 3 1 Figure 3 2 and Figure 3 3 show the steps to configure CRC registers and to perform a CRC calculation CR...

Page 960: ...lculation is Wait till previous completed START CRC engine is busy CRC input data left This is polling based CRC calculation No Yes Write input data to CRCn_WR CRCn_CFG CRCn_POLY CRCn_SEED CRCn_FXOR Y...

Page 961: ...ister Clear CRCn_CFG CIRQ ISR for CRC IRQ Write input data to CRCn_WR START Wait till previous CRC calculation is completed No Yes CRCn_CFG LOCK 0 CRCn_CFG CRCn_POLY CRCn_SEED CRCn_FXOR Configure Sett...

Page 962: ...OCK 0 controller START Wait till previous CRC calculation is completed No Yes CRCn_CFG CRCn_POLY CRCn_SEED CRCn_FXOR Configure Settings for DMA request generation CRCn_CFG CIEN 0 Configure DMA transfe...

Page 963: ...and or byte wise using CRCn_CFG RIBYT before they enter the CRC engine The settings are shown below preliminary input data in CRCn_WR register A7 A0 B7 B0 C7 C0 D7 D0 If the input data size is less t...

Page 964: ...ne The required polynomial is provided by CRCn_POLY register The CRC engine starts its operation once CRCn_WR register is written with the input data 5 CRC engine performance The performance of CRC en...

Page 965: ...0000 0000 0000 0000 0000 S0 S2 00000 Bit reflection The checksum is byte aligned Bit S3 S7 and S8 S31 are 0 1 0 32 S7 S0 S15 S8 S23 S16 S31 S24 Byte aligned checksum swapping 21 0000 0000 S7 S0 S15 S8...

Page 966: ...dance with above coefficients is 0x07 Hex The input output bit reflection is disabled in this example The Programmable CRC registers should be configured as follows for the given values The CRC config...

Page 967: ...Final XOR Register CRCn_FXOR CRC Configuration Register CRCn_CFG CRC Write Register CRCn_WR CRC Read Register CRCn_RD Memory Layout of Programmable CRC Registers Figure 4 1 Memory Layout of Programma...

Page 968: ...LY 13 POLY 12 POLY 11 POLY 10 POLY 9 POLY 8 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE Rp Wp INITIAL_VALUE 0 0 0 1 1 1 0 1 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME POLY 7 POLY 6 POLY 5 POLY 4 PO...

Page 969: ...SEED 14 SEED 13 SEED 12 SEED 11 SEED 10 SEED 9 SEED 8 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE Rp Wp INITIAL_VALUE 1 1 1 1 1 1 1 1 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME SEED 7 SEED 6 SEED 5...

Page 970: ...ET 15 14 13 12 11 10 9 8 BIT_NAME FXOR 15 FXOR 14 FXOR 13 FXOR 12 FXOR 11 FXOR 10 FXOR 9 FXOR 8 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE Rp Wp INITIAL_VALUE 1 1 1 1 1 1 1 1 BIT_OFFSET 7 6...

Page 971: ...1 20 19 18 17 16 BIT_NAME SZ 1 SZ 0 LEN 5 LEN 4 LEN 3 LEN 2 LEN 1 LEN 0 ACCESS_TYPE R W R7W R W R7W R W R W R W R W PROT_TYPE Rp Wp INITIAL_VALUE 1 1 1 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_N...

Page 972: ...triggered when CRCn_CFG CIEN bit is enabled and CRC interrupt flag CRCn_CFG CIRQ is set bit24 CIRQ CRC Interrupt Flag This bit indicates the interrupt status of CRC Bit Description 0 No interrupt req...

Page 973: ...on of the Programmable CRC Note For 8 bit input data this setting has no effect bit9 ROBIT Reflect Output Bits Bit Description 0 Disable output bit reflection 1 Enable output bit reflection The bit or...

Page 974: ...R W R W PROT_TYPE Rp Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME CRCWR 7 CRCWR 6 CRCWR 5 CRCWR 4 CRCWR 3 CRCWR 2 CRCWR 1 CRCWR 0 ACCESS_TYPE R W R W R W R W R W R W R W R W P...

Page 975: ...R W R W R W R W PROT_TYPE Rp Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME CRCRD 7 CRCRD 6 CRCRD 5 CRCRD 4 CRCRD 3 CRCRD 2 CRCRD 1 CRCRD 0 ACCESS_TYPE R W R W R W R W R W R W R...

Page 976: ...Document Number 002 04852 Rev G 975 CHAPTER 26 PCMPWM This chapter explains the function and operation of the PCMPWM module 1 Overview 2 Configuration and Block Diagram 3 Operation of the PCMPWM 4 Reg...

Page 977: ...Optional mono audio output mode A maximum output resolution of 16 bits An output resolution of 12 bits at a sampling frequency of 24 4 kHz at 100 MHz PWM clock An output resolution of 11 bits at s sam...

Page 978: ...These two blocks represent the free running counter and its prescaler used for the PCM to PWM conversion PCM to PWM Converters These blocks represent the actual PCM to PWM conversion units Each channe...

Page 979: ...The following paragraphs describe these modes in detail 1 Low Pass Filter Mode In the low pass filter mode only a single output is used The output drives an audio amplifier with a low pass filter conn...

Page 980: ...t for full H bridge mode Figure 2 4 Simplified Schematic Illustration of Full H Bridge Mode Output Circuit In full H bridge mode the PCMPWM_i_AL signal is again the inverted PCMPWM_i_AH signal whereas...

Page 981: ...M conversion units in mono mode Figure 2 5 Mono Mode In stereo mode each PCM sample consists of a pair of values for the two channels They are written to the module at the same time but the values for...

Page 982: ...the number specified in PCMPWMi_CONTROL FEST a DMA transfer is requested by the PCMPWM module The DMA then may fill up the full number of entries given by PCMPWMi_CONTROL FEST 1 To set up the PCMPWM...

Page 983: ...h channel may be selected The enable bits are PCMPWMi_OCTRL EN0 and PCMPWMi_OCTRL EN1 The output polarity is programmed with PCMPWMi_OCTRL LEVL0 and PCMPWMi_OCTRL LEVL1 If a channel s output is disabl...

Page 984: ...WM conversion process comprises a free running counter and two comparators The counter counts up from zero to a programmable maximum value The maximum value is given by the PCMPWMi_COUNTP register Whe...

Page 985: ...and simplified H bridge mode PCMPWMi_COUNTP COUNTP is set to 0xFFFF and PCMPWMi_PCMOFFS PCMOFFS is set to 0x8000 For full H bridge mode PCMPWMi_COUNTP COUNTP is set to 0x7FFF The diagrams show the val...

Page 986: ...CHAPTER 26 PCMPWM S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 985 Figure 3 2 PCM to PWM Conversion in Simplified H Bridge Mode...

Page 987: ...CHAPTER 26 PCMPWM 986 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G Figure 3 3 PCM to PWM Conversion in Full H Bridge Mode...

Page 988: ...CHAPTER 26 PCMPWM S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 987 Figure 3 4 PCM to PWM Conversion in Full H Bridge Mode with Dead Timer...

Page 989: ...natively the CPU may poll the interrupt status register to determine if there is free space in the FIFO buffer Regardless of how the buffer FIFO is supplied with data samples the PCMPWMi_CONTROL FEST...

Page 990: ...ied to read a PCM data sample from the FIFO buffer when it was empty Instead of a new PCM data sample the PCM to PWM conversion uses the last PCM value instead 3 FIFO Buffer Overflow Error Interrupt T...

Page 991: ...The following registers are available for each instance of the PCMPWM PCMPWM Control Register PCMPWMi_CONTROL PCMPWM Output Control Register PCMPWMi_OCTRL PCMPWM Clock Select Register PCMPWMi_CLKSEL...

Page 992: ...AME Reserved FEST 4 0 ACCESS_TYPE R0 WX R W PROT_TYPE Wp INITIAL_VALUE 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved DOUBLE MODE 1 0 STEREO DBGEN DMAEN ACCESS_TYPE R0 WX R W R W R W R W R W P...

Page 993: ...ple is processed twice by the conversion unit bit12 11 MODE 1 0 Operation Mode This field defines the module s mode of operation Bits Description 00 The module is configured for low pass filter mode 0...

Page 994: ...PCM to PWM conversion starts immediately If the FIFO buffer is empty when the module gets enabled silence is driven on the PWM outputs and the PCM to PWM conversion starts as soon as there are equal...

Page 995: ...OT_TYPE Wp INITIAL_VALUE 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved LEVL1 LEVL0 ACCESS_TYPE R0 WX R W R W PROT_TYPE Wp INITIAL_VALUE 0 1 1 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserve...

Page 996: ..._AH BH are high active and PCMPWM_0_AL BL are low active bit1 EN1 Output Enable Channel 1 This bit enables or disables PWM signal generation on channel 1 Bit Description 0 PCMPWM_1_AH BH AL BL are set...

Page 997: ...VALUE 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VA...

Page 998: ...26 25 24 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0 BIT_OFFSET 15 14 13 12 11...

Page 999: ...31 30 29 28 27 26 25 24 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0 BIT_OFFSET...

Page 1000: ...ALUE 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VAL...

Page 1001: ...bled bit1 OVFL FIFO Overflow Error This bit enables or disables the FIFO overflow error interrupt Bit Description 0 The FIFO overflow error interrupt is disabled 1 The FIFO overflow error interrupt is...

Page 1002: ...te access to the PCMPWMi_INTRCLR register REGISTER_NAME PCMPWMi_INTRSTAT OFFSET 0x00000018 ACCESS_SIZE B H W MULTIPLE 0 NUMERIC_TYPE OTHER BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME Reserved ACCESS_T...

Page 1003: ...nversion block tried to read another PCM data sample but the FIFO buffer is empty bit1 OVFL FIFO Overflow Error This status bit reflects if a FIFO buffer overflow has occurred Bit Description 0 No err...

Page 1004: ...ITIAL_VALUE 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INITIAL_VALUE 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE Wp INIT...

Page 1005: ...bit is always read as 0 bit1 OVFL FIFO Overflow Error When this bit is written as 1 the FIFO overflow error interrupt is cleared Bit Description 0 Leave the FIFO overflow error interrupt unchanged 1...

Page 1006: ...TYPE RN INITIAL_VALUE BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME DATA1 7 0 ACCESS_TYPE RN W PROT_TYPE RN INITIAL_VALUE BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME DATA0 15 8 ACCESS_TYPE RN W PROT_TYPE...

Page 1007: ...ument Number 002 04852 Rev G CHAPTER 27 HyperBus Interface This chapter explains the functionality and operation of the HyperBus interface HYPERBUSI 1 Overview 2 Block Diagram 3 Operation of the HYPER...

Page 1008: ...e Supports operational frequency up to 166MHz Achieves maximum 333MB s data throughput by 8 bits bus and few timing signals only Supports the double data rate interface Supports two slave devices Supp...

Page 1009: ...the burst length to the C A cycle on HyperBus as is Figure 3 1 Read Waveform CA0 47 40 CA0 39 32 CA1 31 24 CA1 23 16 CA0 15 8 CA0 7 0 Dn 7 0 Dn 15 8 Dn 1 7 0 Dn 1 15 8 CSn CK RWDS DQ 7 0 When device s...

Page 1010: ...ata is masked by high of RWDS The HYPERBUSI module puts the transaction request from AXI bus such as the burst type and the burst length to the C A cycle on HyperBus as is Therefore RWDS is determined...

Page 1011: ...CHAPTER 27 HyperBus Interface 1010 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G Figure 3 4 Timing Adjustment CSn CK RCSHI and WCSHI RCSS and WCSS RCSH and WCSH...

Page 1012: ...The Tx Rx Controller accepts the wrap read transaction and compares the required wrap size with the WRAPSIZE in HYPERBUSI_MCRn When the wrap size is the same the Tx Rx Controller requires the wrap bur...

Page 1013: ...on to define the transaction The C A Coder builds a command address information by the request from AXI bus and the register settings Table 3 1 C A Format of HYPERBUSI C A Bit Name Assignment 47 R W 0...

Page 1014: ...in order to receive the burst write transaction without a wait on AXI bus 3 4 3 R DAT FIFO and RX FIFO The RX FIFO is composed of 20 bits width x 256 depth This FIFO is used to store the data which r...

Page 1015: ...ler and is controlled by HYPERBUSI_IEN and INTn signal Please refer to section 4 2 Interrupt Enable Register HYPERBUSIn_IEN and Interrupt Status Register HYPERBUSIn_ISR 3 5 3 GPO Signal GPO signals ar...

Page 1016: ...ignal for controlling memory access 3 6 1 RSTOn RSTOn signal is allocated to external interface in order to connect RSTO of HyperBus memory RSTOn signal is used in order to determine whether AXI trans...

Page 1017: ...he HYPERBUSI Controller Status Register HYPERBUSIn_CSR Interrupt Enable Register HYPERBUSIn_IEN Interrupt Status Register HYPERBUSIn_ISR Memory Base Address Register 0 1 HYPERBUSIn_MBR Memory Configur...

Page 1018: ...BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME RFU RFU RFU RFU RFU RFU RFU WACT ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 1...

Page 1019: ...rite Transaction This bit indicates whether access address is acceptable in the latest write transaction Bit Description 0 Normal operation 1 Access address is not reachable AXI DECERR occurs bit16 WA...

Page 1020: ...scription 0 Normal operation 1 Protocol is not supported AXI SLVERR occurs bit8 RDECERR Decode Error in Read Transaction This bit indicates whether access address is acceptable in the latest read tran...

Page 1021: ...IAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME RFU RFU RFU RFU RFU RFU RFU RFU ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0...

Page 1022: ...ed for Future Use When writing this register this bit should be set to 0 for future compatibility When reading this register this bit is 0 for future compatibility bit0 RPCINTE HyperBus Memory Interru...

Page 1023: ...R0 WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME RFU RFU RFU RFU RFU RFU RFU RFU ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX PROT_TYPE INITIAL_V...

Page 1024: ...CHAPTER 27 HyperBus Interface S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1023 Bit Description 0 No interrupt 1 Interrupt...

Page 1025: ...20 19 18 17 16 BIT_NAME A 23 A 22 A 21 A 20 A 19 A 18 A 17 A 16 ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT...

Page 1026: ...0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME RFU RFU RFU RFU RFU RFU CRMO ACS ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14...

Page 1027: ...e asymmetry cache system Bit Description 0 No asymmetry cache system support 1 Asymmetry cache system support bit5 CRT Configuration Register Target This bit indicates whether access is to memory spac...

Page 1028: ...WCSHI 1 WCSHI 0 ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME RCSS 3 RCSS 2 RCSS 1 RCSS 0 WCSS 3 WCSS 2 WCSS 1 WCSS 0...

Page 1029: ...erts the CK cycles to the chip select high period Bits Description 0000 1 5 CK 0001 2 5 CK 0010 3 5 CK 1111 16 5 CK bit23 20 RCSS 3 0 Read Chip Select Setup to next CK Rising Edge In the read access t...

Page 1030: ...ion 0000 1 CK 0001 2 CK 0010 3 CK 1111 16 CK bit7 4 RFU Reserved for Future Use When writing this register this bit should be set to 0 for future compatibility When reading this register this bit is 0...

Page 1031: ...PE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME RFU RFU RFU RFU RFU RFU RFU RFU ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX...

Page 1032: ...FU RFU RFU RFU RFU ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME RFU RFU RFU RFU RFU RFU RFU RFU ACCESS_...

Page 1033: ...22 21 20 19 18 17 16 BIT_NAME RFU RFU RFU RFU RFU RFU RFU RFU ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_...

Page 1034: ...ual Document Number 002 04852 Rev G 1033 CHAPTER 28 LCD Controller This chapter explains the LCD controller 1 Overview 2 Features 3 Configuration 4 Operation 5 Setting 6 Registers 7 Q A 8 Sample Progr...

Page 1035: ...Furthermore it enables up to 8 element display as static LCD output VRAM0 VRAM15 2 1 Bit3 7 6 5 4 Internal split resistance or external split resistance 0 Timing circuit COM3 Main clock Prescaler LCD...

Page 1036: ...emory Built in 16 byte data memory for display No display selection Enabled Pin COM0 to COM3 SEG0 to SEG31 V0 V1 V2 V3 pins are used for general purpose ports also and switching is enabled SEG23 to SE...

Page 1037: ...ange with PFR and EPFR Pin function change with PFR and EPFR See CHAPTER 11 I O PORTS or VCC Main clock Sub clock FP1 0 LCR0 bit1 0 Disconnect internal split resistance Connect internal split resistan...

Page 1038: ...ion oscillates waveforms that drive the LCD are output to the common segment output pins COM0 to COM3 SEG0 to SEG31 The content of the VRAM is read automatically in synchronization with the timing of...

Page 1039: ...transition to PSS mode LCD display stop when power shutdown 6 Blanking Function Duty drive Light of the LCD can be turned off with selection of non display BK 1 of blanking However non selection wave...

Page 1040: ...put are used for LCD display COM2 output and COM3 output are not used 1 2 Bias Output Waveform Case Liquid crystal elements that have maximum difference in potential between the common output and segm...

Page 1041: ...CHAPTER 28 LCD Controller 1040 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G...

Page 1042: ...CHAPTER 28 LCD Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1041 LCD panel connection case and display data case 1 2 duty drive method...

Page 1043: ...M1 output and COM2 output are used for LCD display COM3 output is not used 1 3 Bias Output Waveform Case Liquid crystal elements that have maximum difference in potential between the common output and...

Page 1044: ...CHAPTER 28 LCD Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1043...

Page 1045: ...CHAPTER 28 LCD Controller 1044 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G LCD panel connection case and display data case 1 3 duty drive method...

Page 1046: ...t COM1 output COM2 output and COM3 output are used for LCD display 1 4 Bias Output Waveform Case For LCD liquid crystal elements that have maximum difference in potential between the common output and...

Page 1047: ...CHAPTER 28 LCD Controller 1046 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G...

Page 1048: ...CHAPTER 28 LCD Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1047 LCD panel connection case and display data case 1 4 duty drive method...

Page 1049: ...T0 to ST8 are used for LCD display Static Drive Output Waveform Case For LCD liquid crystal elements that have maximum difference in potential between the common output and segment output light up Exa...

Page 1050: ...CHAPTER 28 LCD Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1049...

Page 1051: ...CHAPTER 28 LCD Controller 1050 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G LCD panel connection case and display data case Static drive method...

Page 1052: ...le setting LCD control register 0 LCR0 See 7 3 Duty selection activation See 7 5 Display selection See 7 7 Setting Necessary for Cancellation of LCD Display Setting Set Register Set Method Non display...

Page 1053: ...memory for display LDR0 LDR1 See 6 6 Frame cycle setting LCD control register LCRS See 7 3 Setting Necessary for LCD Operation Stop Setting Set Register Set Method LCD operation stop LCD control regi...

Page 1054: ...ster 6 6 Table 6 2 Registers of LCD Port related Register Abbreviation Register Name Reference LCD_KEYCDR key code register 6 7 SEGER Segment output Register 6 8 COMVER Common output V pin control reg...

Page 1055: ...t a clock to be used for this module Bit Operation 0 Main clock 1 Sub clock For the single clock products set 0 bit6 LCEN PSS Timer mode main oscillation operation sub oscillation operation operation...

Page 1056: ...o COM3 When the display mode selection bits MS 1 0 are set to 00 the LCD controller s operation is stopped and the common pin segment pin output L level bit1 bit0 FP1 FP0 Frame cycle FP1 FP0 Frame cyc...

Page 1057: ...G7 VRAM4 SEG8 SEG9 VRAM5 SEG10 SEG11 VRAM6 SEG12 SEG13 VRAM7 SEG14 SEG15 VRAM8 SEG16 SEG17 VRAM9 SEG18 SEG19 VRAM10 SEG20 SEG21 VRAM11 SEG22 SEG23 VRAM12 SEG24 SEG25 VRAM13 SEG26 SEG27 VRAM14 SEG28 SE...

Page 1058: ...t6 bit5 bit4 SEG11 bit3 bit2 bit1 bit0 SEG12 bit3 bit2 bit1 bit0 SEG14 bit7 bit6 bit5 bit4 SEG15 bit7 bit6 bit5 bit4 SEG13 bit3 bit2 bit1 bit0 SEG16 bit7 bit6 bit5 bit4 SEG17 bit3 bit2 bit1 bit0 SEG18...

Page 1059: ...n of the LCDC control register 1 is shown below LCR1 bit 7 6 5 4 3 2 1 0 Field Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Attribute R W1 R W1 R W1 R W1 R W1 R W1 R W1 R W1...

Page 1060: ...LCDCMR bit 7 6 5 4 3 2 1 0 Field DTCH Reserved Reserved Reserved Reserved Reserved Reserved Reserve d Attribute R W R W0 R W0 R W0 R W1 R W1 R W1 R W1 Protection attribute Initial value 0 0 0 0 0 0 0...

Page 1061: ...n 0 Main clock 1 Sub clock For the single clock products set 0 bit6 LCSEN PSS Timer mode main oscillation operation sub oscillation operation operation enable Bit Operation 0 LCD display stop in the P...

Page 1062: ...FPS1 FPS0 Frame Cycle 0 0 For SCSS 0 211 4 FCL For SCSS 1 23 4 FCL 0 1 For SCSS 0 212 4 FCL For SCSS 1 24 4 FCL 1 0 For SCSS 0 213 4 FCL For SCSS 1 25 4 FCL 1 1 For SCSS 0 214 4 FCL For SCSS 1 26 4 F...

Page 1063: ...n of the static LCD display data register is shown below LDR0 bit 15 14 13 12 11 10 9 8 Field ST8 Attribute R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R W Protection attribute Initial value 0 0 0 0 0 0...

Page 1064: ...atic output data ST6 ST6 static output data ST5 ST5 static output data ST4 ST4 static output data ST3 ST3 static output data ST2 ST2 static output data ST1 ST1 static output data ST0 ST0 static output...

Page 1065: ...s KEYCDR bit 31 30 29 28 27 26 25 24 Field KEY1 KEY0 SIZE1 SIZE0 Reserved Attribute R0 W R0 W R0 W R0 W R0 WX R0 WX R0 WX R0 WX Protection attribute Initial value 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18...

Page 1066: ...ting to a key code target register Write the same data to these bits when writing the key codes of 00 01 10 and 11 to KEY 1 0 in this order Bit29 28 Description 0 0 Set byte access 0 1 Set half word a...

Page 1067: ...ain from the beginning When the KEYCDR register is read during writing to KEY 1 0 the key code setting becomes invalid In such cases you need to set the key codes again from the beginning When access...

Page 1068: ...nitial value 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 Field SEGE15 SEGE14 SEGE13 SEGE12 SEGE11 SEGE10 SEGE9 SEGE8 Attribute R W R W R W R W R W R W R W R W Protection attribute Initial value 0 0 0...

Page 1069: ...W R W Protection attribute Initial value 0 0 0 0 0 0 0 0 bit 23 22 21 20 19 18 17 16 Field Reserved Attribute R1 WX R1 WX R1 WX R1 WX R1 WX R1 WX R1 WX R1 WX Protection attribute Initial value 1 1 1...

Page 1070: ...28 VEn n 0 to 2 bit27 24 COMEn n 0 to 3 bit23 0 Reserved The read value is always 1 Writing has no effect on operation VEn n 0 to 2 Operation 0 Disable LCDC reference voltage input 1 Enable LCDC refer...

Page 1071: ...7 How can I Execute Cancel the Display 7 8 How can I Display during the PSS Timer Mode Main Oscillation Operation Sub Oscillation Operation 7 9 How can I Select either Internal or External for the Div...

Page 1072: ...ting ports can be switched to COM SEG output Set pins for COM output and SEG output to peripheral output See following table for pin setting Duty drive Pin V0 V3 and COM and SEG Setting Method Port Se...

Page 1073: ...SEG28 ST5 SEG29 ST6 SEG30 ST7 SEG31 ST8 Static drive COM output and SEG output setting With software setting ports can be switched to COM SEG output Set pins for static drive to peripheral output See...

Page 1074: ...n COM1 COM0 SEG 2n bit1 bit0 SEG 2n 1 bit5 bit4 1 3 Duty Pin COM2 COM1 COM0 SEG 2n bit2 bit1 bit0 SEG 2n 1 bit6 bit5 bit4 1 4 Duty Pin COM3 COM2 COM1 COM0 SEG 2n bit3 bit2 bit1 bit0 SEG 2n 1 bit7 bit6...

Page 1075: ...quency Set 01 213 N Main clock frequency Set 10 214 N Main clock frequency Set 11 N Time division number Value of MS 1 0 1 Frame Cycle When a Sub Clock Is Selected Selection Value Frame Cycle Bits FP...

Page 1076: ...y Mode Selection Bits MS 1 0 N Time Division Number LCD operation stop Pin output L Set 00 To set 1 2 duty output mode Set 01 2 To set 1 3 duty output mode Set 10 3 To set 1 4 duty output mode Set 11...

Page 1077: ...w are available Setting of the blanking selection bit LCR0 BK Control Detail Blanking Selection Bit BK To execute LCD display Set 0 To cancel LCD display A non selection waveform is output to a segmen...

Page 1078: ...For LCD display in the PSS timer mode main oscillation operation sub oscillation operation Set 1 When LCEN 1 please do not stop the clock oscillation which selected by the CSS bit during the transitio...

Page 1079: ...esistor Duty drive Set the LCD drive power control bit LCR0 VSEL Control Detail LCD Drive Power Control Bit VSEL For use of the external division resistor The internal division resistor is disconnecte...

Page 1080: ...external resistor must be connected between Vcc and V3 When the external division resistor is selected Voltage for the LCD drive is set with the external division resistor connected to the power pins...

Page 1081: ...rnal division resistor adjust the voltage V3 by putting a variable resister VR between the outer terminals Vcc and V3 7 13 How can I Block the Current with the External Division Resistor When the LCD...

Page 1082: ...0 and LDR1 ST 7 0 00000000 and set the static drive selection port LCS 3 0 The same potential pulses are output from the static drive pins ST0 to ST8 When the LCD with static drive ST0 to ST8 is swit...

Page 1083: ...VRAM07 IO_VRAM00 0x31 IO_VRAM01 0x32 IO_VRAM02 0x00 IO_VRAM03 0x22 IO_VRAM04 0x32 IO_VRAM05 0x30 IO_VRAM06 0x22 IO_VRAM07 0x32 3 Setting of control register Register name Fixed value LCR1 IO_LCR1 byte...

Page 1084: ...CHAPTER 28 LCD Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1083...

Page 1085: ...RAM00 0x53 IO_VRAM01 0x03 IO_VRAM02 0x30 IO_VRAM03 0x72 IO_VRAM04 0x01 IO_VRAM05 0x37 3 Setting of control register Register name Fixed value LCR1 IO_LCR1 byte 0xFF Set to FF Bias setting LCDCMR IO_LC...

Page 1086: ...CHAPTER 28 LCD Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1085...

Page 1087: ...VRAM03 IO_VRAM00 0x9F IO_VRAM01 0x88 IO_VRAM02 0xB6 IO_VRAM03 0xBC 3 Setting of control register registername bit name Fixed value LCR1 IO_LCR1 byte 0xFF Set to FF Bias setting LCDCMR IO_LCDCMR byte 0...

Page 1088: ...CHAPTER 28 LCD Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1087...

Page 1089: ...DC_OUT Set the LCD controller pin to peripheral output 2 Data setting Register name Data setting LDR0 IO_LDR0 byte 0x00 LDR1 IO_LDR1 byte 0xBC 3 Setting of control register Register name bit name Fixe...

Page 1090: ...he LCD with static drive ST0 to ST8 is switched to non display after reset set LDR0 ST8 0 and LDR1 ST 7 0 00000000 and set the static drive selection port LCS 3 0 The same potential pulses are output...

Page 1091: ...nt Number 002 04852 Rev G CHAPTER 29 Indicator PWM This chapter explains the indicator PWM 1 Overview 2 Configuration and Block Diagram 3 Operation of Indicator PWM 4 Registers 5 Precautions for Using...

Page 1092: ...from among six 6 types of clocks divided by 1 16 64 256 1024 2048 For the count operation an underload reloads from the PWM cycle register and the count is repeated Indicator PWM timer activation is...

Page 1093: ...from the set cycle value upon software trigger activation The first output at that time is the L level If the 16 bit down counter matches the set value in the duty setting register the output is inver...

Page 1094: ...tting the software trigger ICNTCR STRG 1 As soon as the software setting is configured the timer status becomes timer count operation in progress ICNTCR DOP 1 Figure 3 2 Timing Chart When Indicator PW...

Page 1095: ...er status PWM output maintains the output status as during timer count stop Figure 3 3 Timing Chart while Timer Count Operation is Stopped 4T 3TR T Main oscillator clock cycle TR Register clock cycle...

Page 1096: ...PCSR and PWM duty setting register IPDUT and updates the count value and duty setting However allow a time of at least 8T T main oscillator clock cycle before setting a second software trigger Failure...

Page 1097: ...Q_IND Table 3 1 Interrupt Control Bits and Interrupt Factors Status Control Register ISTC Interrupt Request Flag Bit Interrupt Request Enable Bit Interrupt Factor Interrupt Factor Output Signal Indica...

Page 1098: ...unt value PWM output waveform Interrupt 0x0003 0x0001 0x0002 0x0000 0x0003 0x0002 Start up edge Duty match DTIR Underfolw UDIR 0xXXXX DOP STRG Figure 1 1 shows the interrupt factors and a timing chart...

Page 1099: ...Count Figure 3 6 Select count clock Clear interrupt flag Enable interrupts Setting PWM count value Setting duty value Various settings Count enable by using CTEN bit Continuous operation Start down c...

Page 1100: ...mber 002 04852 Rev G 1099 3 6 2 Operation Flowchart Count Stop Figure 3 7 During down count Underflow occurs Set UDIR flag Duty matches Set DTIR flag Stop count DOP 0 END Continued from Setting Count...

Page 1101: ...Register List Abbreviated Register Name Register Name Reference ITMCR Timer control register 4 1 ICNTCR Count control register 4 2 ISTC Status control register 4 3 ISTCC Status control clear register...

Page 1102: ...T_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX...

Page 1103: ...is a reserved bit Writing data to these bits has no effect on operation bit10 PMSK Pulse output mask bit This bit controls the output waveform level of the PWM output waveform When the bit is 0 the PW...

Page 1104: ...PWM S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1103 Bit Description 0 Normal polarity 1 Inverse polarity bit2 0 Reserved These are reserved bits Writing data to these bits has no...

Page 1105: ...3 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0...

Page 1106: ...ta to these bits has no effect on operation bit1 CTEN Count operation enable bit This bit enables operation of the down counter If 0 is written to this bit while a counter operation is in progress DOP...

Page 1107: ...0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX PROT_TYPE INITI...

Page 1108: ...is issued to the CPU Writing 1 to the ISTCC UDIEC bit clears this bit Writing 1 to the ISTCS UDIES bit sets this bit Bit Description 0 Disable interrupt requests 1 Enable interrupt requests bit3 2 Res...

Page 1109: ...0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX PROT_TYPE...

Page 1110: ...TC UDIE bit is cleared to 0 0 is always read from this bit Bit Description 0 Disabled 1 Clear the UDIE bit bit3 2 Reserved These are reserved bits Writing data to these bits has no effect on operation...

Page 1111: ...0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX PROT_TYPE INITIAL...

Page 1112: ...C DTIE bit is set to 1 0 is always read from this bit Bit Description 0 Disabled 1 Set the DTIE bit bit4 UDIES Underflow interrupt request enable set bit If 1 is written to this bit the ISTC UDIE bit...

Page 1113: ...rved Reserved Reserved Reserved ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME IPCSR 15 IPCSR 14 IPCSR 13...

Page 1114: ...0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX R0 WX PROT_TYPE INITI...

Page 1115: ...output for normal polarity is all H and the output for inverse polarity is all L If IPCSR IPDUT in the set values the output for normal polarity is all L and the output for inverse polarity is all H...

Page 1116: ...ion is in progress ICNTCR DOP 1 Be sure to stop the count ICNTCR DOP 0 before configuring these settings If the interrupt request flag set timing and clear timing overlap the flag set has priority and...

Page 1117: ...ies Hardware Manual Document Number 002 04852 Rev G CHAPTER 30 FPD Link Converter This chapter explains FPD Link Converter 1 Overview 2 Configuration and Block Diagram 3 Operation 4 Registers CODE FPD...

Page 1118: ...6 0 RX0_2 6 0 RX0_3 6 0 RX0_4 6 0 from to Register APB RX1_0 6 0 RX1_1 6 0 RX1_2 6 0 RX1_3 6 0 RX1_4 6 0 CH_SEL reg CH dsp0_clock_out GDCCR reg GRST GDC Reset from System Control Unit oGRSTX iPCLK iPR...

Page 1119: ...IN0 6 0 TXOUT0P TXOUT0P TxDOUT0 TXOUT0M TXOUT0M TxDOUT0 TX1 6 0 TXIN1 6 0 TXOUT1P TXOUT1P TxDOUT1 TXOUT1M TXOUT1M TxDOUT1 TX2 6 0 TXIN2 6 0 TXOUT2P TXOUT2P TxDOUT2 TXOUT2M TXOUT2M TxDOUT2 TX3 6 0 TXIN...

Page 1120: ...ed PSLVERR The conditions below are when this module will return a slave error 1 Reserved address without a register area access 2 Byte Hword access of an area of register reserved bits only 3 In the...

Page 1121: ...DISN Control FPD Link external output enable disable RSTN Control the FPD Link serializer PLLRSTN Control PLL reset of the FPD Link external output section PWD12N Control the FPD Link 1 2V line power...

Page 1122: ...nual Document Number 002 04852 Rev G 1121 3 4 2 Power DOWN Sequence This section shows power down sequence of FPD Link Figure 3 2 Power down sequence of FPD Link DISN Trm PWD33N RSTN PLLRSTN PWD12N Tr...

Page 1123: ...8 CTRL1 Control1 Register Adjusts FPD Link external output 0x000C Reserved PSLVERR 0x0010 CH_SEL Input Channel select register 0x0014 TX0 CONF TX0 Configuration register 2 3 address access generates P...

Page 1124: ...IPLE 0 31 NUMERIC_TYPE OTHER BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME UNLOCK 31 UNLOCK 30 UNLOCK 29 UNLOCK 28 UNLOCK 27 UNLOCK 26 UNLOCK 25 UNLOCK 24 ACCESS_TYPE R W R W R W R W R W R W R W R W PRO...

Page 1125: ...FPD Link Converter 1124 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G Controls LOCK UNLOCK Bit 31 0 Description 0xB3B0BcB4 UNLOCK Oher LOCK Reading this bit in the LOCK state returns...

Page 1126: ...CCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R W PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 1 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Rese...

Page 1127: ...5 9 Reserved Always write 0 to this bit The read value is 0 bit8 ENABLE Output Enable Controls FPD Link external output enable disable Bit Description 0 Disable default Differential Hi Z output 1 Enab...

Page 1128: ...3 22 21 20 19 18 17 16 BIT_NAME Reserved Reserved VCSEL1 VCSEL0 Reserved VDSEL2 VDSEL1 VDSEL0 ACCESS_TYPE R0 W0 R0 W0 R W R W R0 W0 R W R W R W PROT_TYPE Wp INITIAL_VALUE 0 0 0 1 0 1 0 1 BIT_OFFSET 15...

Page 1129: ...near or above the selected loop filter corner frequency it is possible to select an alternate corner frequency This allows the PLL to filter more of the power supply noise Note that these higher loop...

Page 1130: ...rted Note See the S6J3200 Series datasheet for detailed specification bit15 8 Reserved Always write 0 to this bit The read value is 0 bit7 6 FRANGE These bits select by the TXCLK frequency Bit Referen...

Page 1131: ...served Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT...

Page 1132: ...ed Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved IMD_DAT6 IMD_DAT...

Page 1133: ...ng of the Inversion function of the data selected by RX_NUM Bit Description 0 Disable default 1 Enable bit3 Reserved Always write 0 to this bit The read value is 0 bit2 0 RX_NUM 2 0 RX number Selects...

Page 1134: ...Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved ACCESS_TYPE R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 R0 W0 PROT_TYPE Wp INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11...

Page 1135: ...CHAPTER 30 FPD Link Converter 1134 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G Bit Description 0 Release reset default 1 Set reset...

Page 1136: ...Memory Protection Unit for AXI This chapter explains the functions and operations of the Memory Protection Unit for AMBA AXI protocol bus MPU AXI 1 Overview 2 Configuration and Block Diagram 3 Operat...

Page 1137: ...ged using Non Maskable Interrupt MPU AXI also collects information about the unauthorized bus access and stores it in its internal registers Each of the eight regions in MPU AXI is specified using cor...

Page 1138: ...then applies permissions based on the region match It signals any permission violation to CSR logic that in turn generates NMI interrupt All transactions on AXI master interfaces including the transf...

Page 1139: ...following features Separate address or control and data phases Burst based transaction where only start address is issued Separate write and read address control channels Separate write and read data...

Page 1140: ...on match For FIXED type of burst Lowest address Highest address Burst start address For INCR type of burst Lowest address Burst start address Highest address Burst start address num_bytes x num_transf...

Page 1141: ...s in non privileged mode would generate memory protection violation 010 read write read only Reads and writes are permitted in privileged mode Only reads are permitted in non privileged mode Writes in...

Page 1142: ...tioned in point 2 here happens for multiple regions due to region overlapping Figure 3 2 Example Region Overlapping MPU AXI finds region match signals based on lowest address of AXI burst transaction...

Page 1143: ...otection Logic All transactions on the AXI master interfaces are monitored and checked for permitted access Bus monitor and protection logic within MPU AXI compares the lowest address and highest addr...

Page 1144: ...ry space are blocked and MPU AXI does the following actions Burst type signal is driven to FIXED type burst Burst address is driven to predefined FIXED address Privileged Mode Overwrite Feature Option...

Page 1145: ...le for MPU AXI MPU AXI Control Register MPUXn_CTRL0 MPU AXI NMI Enable Register MPUXn_NMIEN MPU AXI Write Error Control Register MPUXn_WERRC MPU AXI Write Error Address Register MPUXn_WERRA MPU AXI Re...

Page 1146: ...0000 01111111 0x0000003C MPUXn_CTRL4 00000000 00000000 00000000 00000000 0x00000040 MPUXn_SADDR4 00000000 00000000 00000000 00000000 0x00000044 MPUXn_EADDR4 00000000 00000000 00000000 01111111 0x00000...

Page 1147: ...ument Number 002 04852 Rev G Offset 3 2 1 0 0x00000070 MPUXn_SADDR8 00000000 00000000 00000000 00000000 0x00000074 MPUXn_EADDR8 00000000 00000000 00000000 01111111 0x00000078 MPUXn_UNLOCK 00000000 000...

Page 1148: ...0 R0 R0 R0 R0 RWP RWP RWP R0 R0 R0 R0 R0 R0 RWP R R0 R0 R0 RWP RWP RWP R R R0 R0 R0 R0 R0 R0 R0WP R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 Bit Position Bit Field Name Bit Desc...

Page 1149: ...AXI is stopped i e MPUXn_CTRL0 MPUSTOPEN 1 and MPU stop input is asserted All accesses on AXI master memory write or read address channel are converted to FIXED type burst with predefined address Note...

Page 1150: ...ad0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 NMIEN R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R...

Page 1151: ...0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X X X 0 Bit Position Bit Field Name Bit Description 31 16 read0 15 11...

Page 1152: ...12 11 10 09 08 07 06 05 04 03 02 01 00 AWADDR 31 AWADDR 30 AWADDR 29 AWADDR 28 AWADDR 27 AWADDR 26 AWADDR 25 AWADDR 24 AWADDR 23 AWADDR 22 AWADDR 21 AWADDR 20 AWADDR 19 AWADDR 18 AWADDR 17 AWADDR 16 A...

Page 1153: ...0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R R R R R R R R R R R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X X X X X X X X X X 0 Bit Position Bit Field Name Bit Description 31 16 read0 15 11...

Page 1154: ...12 11 10 09 08 07 06 05 04 03 02 01 00 ARADDR 31 ARADDR 30 ARADDR 29 ARADDR 28 ARADDR 27 ARADDR 26 ARADDR 25 ARADDR 24 ARADDR 23 ARADDR 22 ARADDR 21 ARADDR 20 ARADDR 19 ARADDR 18 ARADDR 17 ARADDR 16 A...

Page 1155: ...0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Position Bit Field Name Bit Description 31 16 read0 15 11 read0 10 8 AP Access Permissions These bits are used to control access permissions for region 1 7 2 read0 1 MPU...

Page 1156: ...2 11 10 09 08 07 06 05 04 03 02 01 00 SADDR 31 SADDR 30 SADDR 29 SADDR 28 SADDR 27 SADDR 26 SADDR 25 SADDR 24 SADDR 23 SADDR 22 SADDR 21 SADDR 20 SADDR 19 SADDR 18 SADDR 17 SADDR 16 SADDR 15 SADDR 14...

Page 1157: ...11 10 09 08 07 06 05 04 03 02 01 00 EADDR 31 EADDR 30 EADDR 29 EADDR 28 EADDR 27 EADDR 26 EADDR 25 EADDR 24 EADDR 23 EADDR 22 EADDR 21 EADDR 20 EADDR 19 EADDR 18 EADDR 17 EADDR 16 EADDR 15 EADDR 14 E...

Page 1158: ...R0WP R0WP R0WP R0WP R0WP R0WP R0WP R0WP R0WP R0WP R0WP R0WP R0WP R0WP R0WP R0WP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Position Bit Field Name Bit Description 31 0 UNLOCK...

Page 1159: ...D 28 MID 27 MID 26 MID 25 MID 24 MID 23 MID 22 MID 21 MID 20 MID 19 MID 18 MID 17 MID 16 MID 15 MID 14 MID 13 MID 12 MID 11 MID 10 MID 9 MID 8 MID 7 MID 6 MID 5 MID 4 MID 3 MID 2 MID 1 MID 0 R R R R R...

Page 1160: ...otection violation on the bus Therefore once an NMI interrupt flag is set the further monitoring of AXI master interface is stalled until MPUXn_CTRL0 NMI bit is cleared This implies that any protectio...

Page 1161: ...bit have no visible impact on the state of this bit 3 When the NMI is triggered or is in polling mode if the software detects during its polling cycle that the MPUXn_CTRL0 NMI status flag is set the C...

Page 1162: ...AHB This chapter explains the function and operation of the Memory Protection Unit for the AMBA Advanced High Speed Bus MPU AHB in the Next Generation Microcontrollers 1 Overview 2 Configuration and...

Page 1163: ...zed bus access and stores it in its internal registers The features of the MPU AHB module are listed in this section Each of the eight regions in MPU AHB is specified using corresponding start address...

Page 1164: ...s It finds out the region s where the current transfer belongs to and then applies permissions based on the region match It signals any permission violation using an NMI interrupt All transfers on the...

Page 1165: ...lowest priority region The Start Address specifies the first address of the region and is specified by registers MPUHn_SADDR1 to MPUHn_SADDR8 for region 1 to region 8 respectively Since the region gra...

Page 1166: ...e MPU AHB only supports Single Transfer Monitoring and not AHB Burst Monitoring Therefore it can only be used together with AHB Masters that do not request Burst transfers Figure 3 1 Example Region Ov...

Page 1167: ...te a memory protection violation 010 Read write Read only Reads and writes are permitted in privileged mode Only reads are permitted in non privileged mode Writes in non privileged mode would generate...

Page 1168: ...The address and control information of the current transfer is stored in MPUHn_MERRA and MPUHn_MERRC respectively All further transfers are blocked until the MPUHn_CTRL0 NMI flag is cleared by softwar...

Page 1169: ...The following registers are available for the MPU AHB MPU AHB Control Register MPUHn_CTRL0 MPU AHB NMI Enable Register MPUHn_NMIEN MPU AHB Memory Error Control Register MPUHn_MERRC MPU AHB Memory Erro...

Page 1170: ...SADDR4 00000000 00000000 00000000 00000000 0x0000003C MPUHn_EADDR4 00000000 00000000 00000000 00011111 0x00000040 MPUHn_CTRL5 00000000 00000000 00000000 00000000 0x00000044 MPUHn_SADDR5 00000000 00000...

Page 1171: ...200 Series Hardware Manual Document Number 002 04852 Rev G Offset 3 2 1 0 0x0000006C MPUHn_EADDR8 00000000 00000000 00000000 00011111 0x00000070 MPUHn_UNLOCK 00000000 00000000 00000000 00000000 0x0000...

Page 1172: ...PEN MPUSTOP LST read0 read0 read0 read0 read0 read0 NMICL NMI R0 R0 R0 R0 R0 RWP RWP RWP R0 R0 R0 R0 R0 R0 R0WP R R0 R0 R0 RWP RWP RWP R R R0 R0 R0 R0 R0 R0 R0WP1 R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 1173: ...ure is enabled This bit together with MPU STOP input controls the STOP status of MPU AHB 9 MPUSTOP MPU STOP Status 0 MPU AHB is not in STOP mode 1 MPU AHB is in STOP mode i e MPUSTOPEN 1 and MPU STOP...

Page 1174: ...read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 NMIEN R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R0 R...

Page 1175: ...read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 read0 HPROT HWRITE R0 R0...

Page 1176: ...6 05 04 03 02 01 00 HADDR 31 HADDR 30 HADDR 29 HADDR 28 HADDR 27 HADDR 26 HADDR 25 HADDR 24 HADDR 23 HADDR 22 HADDR 21 HADDR 20 HADDR 19 HADDR 18 HADDR 17 HADDR 16 HADDR 15 HADDR 14 HADDR 13 HADDR 12...

Page 1177: ...0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Position Bit Field Name Bit Description 31 16 read0 15 11 read0 10 8 AP Access Permissions These bits are used to control access permi...

Page 1178: ...7 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 SADDR 31 SADDR 30 SADDR 29 SADDR 28 SADDR 27 SADDR 26 SADDR 25 SADDR 24 SADDR 23 SADDR 22 SADDR 21 SADDR 20 SADDR 19...

Page 1179: ...5 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 EADDR 31 EADDR 30 EADDR 29 EADDR 28 EADDR 27 EADDR 26 EADDR 25 EADDR 24 EADDR 23 EADDR 22 EADDR 21 EADDR 20 EADDR 19 EADDR...

Page 1180: ...P R0WP R0WP R0WP R0WP R0WP R0WP R0WP R0WP R0WP R0WP R0WP R0WP R0WP R0WP 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit Position Bit Field Name Bit Description 31 0 UNLOCK MPU AHB...

Page 1181: ...MID 30 MID 29 MID 28 MID 27 MID 26 MID 25 MID 24 MID 23 MID 22 MID 21 MID 20 MID 19 MID 18 MID 17 MID 16 MID 15 MID 14 MID 13 MID 12 MID 11 MID 10 MID 9 MID 8 MID 7 MID 6 MID 5 MID 4 MID 3 MID 2 MID...

Page 1182: ...ndependent of the values read from the reserved register bits The MPU AHB supports storage of information of the first memory protection violation only on the bus Therefore once an NMI interrupt flag...

Page 1183: ...mode is desired the software can reset the MPUHn_NMIEN NMIEN bit to 0 Note The MPUHm_NMIEN NMIEN can be written only once after reset Subsequent write accesses to this bit have no visible impact on th...

Page 1184: ...he status registers it shall clear the MPUHn_CTRL0 NMI flag by writing 1 to the MPUHn_CTRL0 NMICL bit Clearing the MPUHn_CTRL0 NMI flag ensures that the MPU AHB starts monitoring the AHB Master Interf...

Page 1185: ...Document Number 002 04852 Rev G CHAPTER 33 Graphics Subsystem This chapter explains Graphics Subsystem 1 Overview 2 Configuration and Block Diagram 3 Operation of the Graphics Subsystem 4 Registers 5...

Page 1186: ...xture YCbCr420 texture Compressed texture FJ_COMP compressed texture ETC2 EAC texture Palette texture Automatic texture generation Luminescent texture gradient texture BitBlt bit block transfer Resolu...

Page 1187: ...1 Block Diagrams Figure 2 1 Block Diagram of the Graphics Subsystem MPU MPU MPU BLIT Engine Drawing Engine Bus Monitor Command Sequencer MPU 3D Graphics Core MPU MPU 2D Graphics Core To From Main Syst...

Page 1188: ...Buffer access 1 3D Graphics Core Scene Buffer access 2 3D Graphics Core Copy Area operation The following write masters do not have an Memory Protection Units Main system port Use the Memory Protectio...

Page 1189: ...ics Core bandwidth critical 3rd read port All read masters of the 3D Graphics Core Configurable priority for each port or Round Robin arbitration Arbitration not on burst but single memory access leve...

Page 1190: ...ComCtrl_SW2 ComCtrl_SW3 IRQ 2D Graphics Core ContentStream0_2DGC ExtDst0_ShdLoad ExtDst0_FrameComplete ExtDst0_SeqComplete FrameGen0_SecSync_On FrameGen0_SecSync_Off FrameGen0_Int1 IRQ 2D Graphics Cor...

Page 1191: ...Core Histogram_2DGC Histogram4_ShdLoad Histogram4_Valid IRQ DDRHSSPI interface DDRHSSPI DDRHSSPI_Tx DDRHSSPI_Rx IRQ 3D Graphics Core SRUI_3DGC Shadow Register Updated IRQ 3D Graphics Core LINI_3DGC L...

Page 1192: ...800 Reserved do not use 5021_2000 0000_0400 High Speed HS SPI configuration See 2 5021_2400 0000_0C00 Reserved do not use 5021_3000 0000_1000 Reserved do not use 5021_4000 0000_0400 Reserved do not us...

Page 1193: ...ck key 0x112ABB56 for MPUs 0x5651F763 for others Enable all access protection unlock key 0xACCABB56 for MPUs 0x691DB936 for others Disable all access protection privilege key 0xAEE95CDC Enable non pri...

Page 1194: ...uration clock can be changed at any time e g also when transfers are in progress but note that configuration access bandwidth and latency are greatly influenced by this setting 3 1 2 Display Clock Set...

Page 1195: ...e error_constant can be taken from the following table Table 33 4 Error Constants Values Center Spread Down Spread Sinus modulation 4096 2048 Saw tooth modulation 8192 4096 The amplitude is the amplit...

Page 1196: ...isplay clock for display clock output is only allowed if the 2D Graphics Core DisEngCfg ClockCtrl setting is set to DIV2 Display Clock Shift To allow to create sufficient margin for setup and hold tim...

Page 1197: ...ol unit Note The content of this register can be changed by program Register Protection For the 2D Graphics Core configuration register refer to 1 The SubsysCtrl and High Performance Bus Matrix regist...

Page 1198: ...pt control functionality enable status clear is implemented at the Bus Monitor registers MonitorInterruptEnable Clear and ErrorType status Interrupts from Memory Protection Units Interrupt control fun...

Page 1199: ...ilable for HyperBusTM interface 1 Setup registers StartMaster1Region to use some that available space for HyperBusTM interface 1 Setup register field remap to 1 to select HyperBus for the external mem...

Page 1200: ...ata from the 3D Graphics Core setup the interrupt 2 as follows Set Int2Col to 1 Set Int2HsEn to 1 Set Int2En to 1 Include setup of the 3D Graphics Core and ExtSrc8 in the step 1 or step 2 Prepare disp...

Page 1201: ...egisters Enable the 3D Graphics Core by setting the EN bit of BRONTES_CFG register to 1 To wait until the shadows are loaded poll the UPD bit in BRONTES_UPD register until it becomes 0 again Setup Ext...

Page 1202: ...NTES_CFG register to 1 To wait until the shadows are loaded poll the UPD bit in BRONTES_UPD register until it becomes 0 again Setup ExtSrc8 accordingly Set all extsrc8_ColorComponentBits register fiel...

Page 1203: ...3D Graphics Core Area Address range 2D Graphics Core 3D Graphics Core External Flash Memory 0x40000000 0x4FFFFFFF Read Only Read Only Internal video RAM 0x50000000 0x501FFFFF Read Write Read Write Th...

Page 1204: ...te access to the lock unlock register with an invalid key value a valid key value when the freeze status is active the lock key value when internal unlock counter is 15 the privilege key value when th...

Page 1205: ...y 0x1021_4000 0x005C Read only 0x1021_4000 0x0060 Read only 0x1021_4000 0x0064 Read only 0x1021_4000 0x0068 0x00000000 0x1021_4000 0x006C Read only 0x1021_4000 0x0070 Read only 0x1021_4000 0x0074 Read...

Page 1206: ...0x44104 0x00000000 0x1040_0000 0x44108 0x00000000 0x1040_0000 0x45100 0x00000000 0x1040_0000 0x45104 0x00000000 0x1040_0000 0x45108 0x00000000 0x1040_0000 0x46100 0x00000000 0x1040_0000 0x46104 0x000...

Page 1207: ...0000000 0x1040_0000 0x52104 0x00000000 0x1040_0000 0x52108 0x00000000 0x1040_0000 0x53100 0x00000001 0x1040_0000 0x53104 0x00000001 0x1040_0000 0x53108 0x00000000 0x1040_0000 0x54100 0x00000001 0x1040...

Page 1208: ...ad access is possible to all registers of this address block When privilege protection is active only privileged read and write access is possible Both protections can be active at the same time BIT_O...

Page 1209: ...ey 0x5651F763 Decrements the unlock counter When the counter value is null lock protection is active Reset counter value is 1 unlock_key 0x691DB936 Increments the unlock counter Max allowed value is 1...

Page 1210: ...SET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved FreezeStatus ACCESS_TYPE R0 WX R WX PROT_TYPE...

Page 1211: ...6J3200 Series Hardware Manual Document Number 002 04852 Rev G Bit Description 0 inactive 1 active bit0 LockStatus Lock Status Current freeze status Bit Description 0 protection status can be changed 1...

Page 1212: ...PApplication IPFeatureSet ACCESS_TYPE R W R W PROT_TYPE RpL WpL INITIAL_VALUE 0 1 0 0 0 1 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME IPEvolution DesignMaturityLevel ACCESS_TYPE R W R W PROT_TYPE Rp...

Page 1213: ...ure Link 4 BlitDisplayCaptureDrawing Blit and Drawing Engine Display and Capture Controller bit19 16 IPFeatureSet IP Feature Set Bit Description 1 ECO 2 LIGHT 3 STANDARD 4 PLUS 5 EXTENSIVE bit15 12 IP...

Page 1214: ...0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 WX PRO...

Page 1215: ...CCESS_TYPE R0 WX PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 7 6 5 4...

Page 1216: ...se an error response and no change to the enable Bit Description 0 The non maskable interrupt is disabled and only the InterruptStatus register can be used to see the status 1 The non maskable interru...

Page 1217: ...ET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE RX WX PROT_TYPE WpL INITIAL_VALUE BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE RX WX PROT_TYPE WpL INITIAL_VALUE BIT_OFFSET 7...

Page 1218: ...RAM ECC Display non maskable Interrupt Preset Bit Written Description 0 Ignored 1 Non maskable interrupt request will be raised bit0 VRamInterruptECCBlitDrawCmdSysPreset VRAM ECC 2D Graphics Core non...

Page 1219: ...pL INITIAL_VALUE BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE RX WX PROT_TYPE WpL INITIAL_VALUE BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE RX WX PROT_TYPE WpL I...

Page 1220: ...leared bit1 VRamInterruptECCDispClear VRAM ECC Display non maskable Interrupt Clear Bit Written Description 0 Ignored 1 Non maskable interrupt request will be cleared bit0 VRamInterruptECCBlitDrawCmdS...

Page 1221: ...2 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL INITIAL_VALUE 0 0...

Page 1222: ...s VRAM ECC Display non maskable Interrupt Status Bit Description 0 ECC single bit error condition is not reported 1 ECC single bit error condition is reported bit0 VRamInterruptECCBlitDrawCmdSysStatus...

Page 1223: ...of this address block When privilege protection is active only privileged read and write access is possible Both protections can be active at the same time BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME...

Page 1224: ...lock_key 0x5651F763 Decrements the unlock counter When the counter value is null lock protection is active Reset counter value is 1 unlock_key 0x691DB936 Increments the unlock counter Max allowed valu...

Page 1225: ...0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved dsp_Freeze Status ACCESS_TYPE R0 WX...

Page 1226: ...Rev G 1225 bit4 dsp_PrivilegeStatus display Privilege Status Current status of privilege protection Bit Description 0 inactive 1 active bit0 dsp_LockStatus display Lock Status Current freeze status Bi...

Page 1227: ...TYPE R W PROT_TYPE RpL WpL INITIAL_VALUE 1 1 1 1 0 0 0 0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 bit23 8 dsp0_ ClockDivider displ...

Page 1228: ...DSP_CLK_max fREF_CLK 2 x int dsp0 1_ClockDivider With DIVIDER fREF_CLK fDSP_CLK In case of RSDS Also unless the clock divider implemented is an integer the duty cycle of the display clock is not 50 Th...

Page 1229: ...IT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved dsp0_ Software Reset ACCESS_TYPE R0 WX R W PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 1 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS...

Page 1230: ...229 This field will only have an effect when field ClockEnable is set to 1 bit0 dsp0_ClockEnable display0 Clock Enable Bit Description 0 Disabling the display clock generation 1 Enabling the display c...

Page 1231: ...If the 2D Graphics Core display clock settings is set to DIV1 the display output must not be used only the display bypass output can be used then These settings will not affect the display bypass out...

Page 1232: ...fset Sets the offset in reference clock cycles for the display clock output with reference to the data output This has to be smaller than the integer part of ClockDivider bit0 dsp0_ClockInvert display...

Page 1233: ...E WpL INITIAL_VALUE BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE RX WX PROT_TYPE WpL INITIAL_VALUE BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE RX WX PROT_TYPE Wp...

Page 1234: ...BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0...

Page 1235: ...dsp0_MeasurementNoCapClkError display0 No Capture Clock Error The value of this field is valid when dsp0_MeasurementReady becomes 1 after a measurement is completed Bit Description 0 The capture clock...

Page 1236: ...dsp0_MeasurementResult 7 0 ACCESS_TYPE R WX PROT_TYPE RpL INITIAL_VALUE 1 1 1 1 1 1 1 1 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL INITIAL_VALUE 0 0 0 0 0 0 0 0 bit2...

Page 1237: ...L WpL INITIAL_VALUE 1 1 1 1 0 0 0 0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 bit23 8 dsp1_ ClockDivider display1 Clock Divider Fix...

Page 1238: ...T_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved dsp1_ Software Reset ACCESS_TY...

Page 1239: ...ational 1 Keeping the display clock domain in reset state Note This field will only have an effect when field ClockEnable is set to 1 bit0 dsp1_ClockEnable display1 Clock Enable Bit Description 0 Disa...

Page 1240: ...If the 2D Graphics Core display clock settings is set to DIV1 the display output must not be used only the display bypass output can be used then These settings will not affect the display bypass out...

Page 1241: ...fset Sets the offset in reference clock cycles for the display clock output with reference to the data output This has to be smaller than the integer part of ClockDivider bit0 dsp1_ClockInvert display...

Page 1242: ...E WpL INITIAL_VALUE BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE RX WX PROT_TYPE WpL INITIAL_VALUE BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE RX WX PROT_TYPE Wp...

Page 1243: ...T_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 B...

Page 1244: ...dsp1_MeasurementNoCapClkError display1 No Capture Clock Error The value of this field is valid when dsp1_MeasurementReady becomes 1 after a measurement is completed Bit Description 0 The capture clock...

Page 1245: ...dsp1_MeasurementResult 7 0 ACCESS_TYPE R WX PROT_TYPE RpL INITIAL_VALUE 1 1 1 1 1 1 1 1 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL INITIAL_VALUE 0 0 0 0 0 0 0 0 bit2...

Page 1246: ...hen privilege protection is active only privileged read and write access is possible Both protections can be active at the same time BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME vram_LockUnlock 31 24 A...

Page 1247: ...rements the unlock counter When the counter value is null lock protection is active Reset counter value is 1 unlock_key 0x691DB936 Increments the unlock counter Max allowed value is 15 privilege_key 0...

Page 1248: ...0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved vram_ Freeze Status ACCE...

Page 1249: ...ription 1 active unlock counter 0 bit4 vram_PrivilegeStatus VRAM Privilege Status Current status of privilege protection Bit Description 0 inactive 1 active bit0 vram_LockStatus VRAM Lock Status Curre...

Page 1250: ...9 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved vram_sram_select 11 8 ACCESS_TYPE R0 WX R W PROT_TYPE...

Page 1251: ...0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME vram_errinj_data_s0_hi 23 16 ACCESS_TYPE R W PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME vram_errinj_data...

Page 1252: ...0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME vram_errinj_data_s0_lo 23 16 ACCESS_TYPE R W PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME vram_errinj_data...

Page 1253: ...20 19 18 17 16 BIT_NAME Reserved vram_errinj_ecc_s0_hi 19 16 ACCESS_TYPE R0 WX R W PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME vram_errinj_ecc_s0_hi 15 8...

Page 1254: ...1 20 19 18 17 16 BIT_NAME Reserved vram_errinj_ecc_s0_lo 19 16 ACCESS_TYPE R0 WX R W PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME vram_errinj_ecc_s0_lo 15...

Page 1255: ...0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME vram_errinj_data_s1_hi 23 16 ACCESS_TYPE R W PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME vram_errinj_data...

Page 1256: ...0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME vram_errinj_data_s1_lo 23 16 ACCESS_TYPE R W PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME vram_errinj_data...

Page 1257: ...20 19 18 17 16 BIT_NAME Reserved vram_errinj_ecc_s1_hi 19 16 ACCESS_TYPE R0 WX R W PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME vram_errinj_ecc_s1_hi 16 8...

Page 1258: ...1 20 19 18 17 16 BIT_NAME Reserved vram_errinj_ecc_s1_lo 19 16 ACCESS_TYPE R0 WX R W PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME vram_errinj_ecc_s1_lo 15...

Page 1259: ...0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME vram_errinj_data_s2_hi 23 16 ACCESS_TYPE R W PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME vram_errinj_data...

Page 1260: ...0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME vram_errinj_data_s2_lo 23 16 ACCESS_TYPE R W PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME vram_errinj_data...

Page 1261: ...20 19 18 17 16 BIT_NAME Reserved vram_errinj_ecc_s2_hi 19 16 ACCESS_TYPE R0 WX R W PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME vram_errinj_ecc_s2_hi 15 8...

Page 1262: ...1 20 19 18 17 16 BIT_NAME Reserved vram_errinj_ecc_s2_lo 19 16 ACCESS_TYPE R0 WX R W PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME vram_errinj_ecc_s2_lo 15...

Page 1263: ...RpL INITIAL_VALUE 1 1 1 1 1 1 1 1 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME vram_sberraddr_s0 23 16 ACCESS_TYPE R WX PROT_TYPE RpL INITIAL_VALUE 1 1 1 1 1 1 1 1 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_...

Page 1264: ...RpL INITIAL_VALUE 1 1 1 1 1 1 1 1 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME vram_sberraddr_s1 23 16 ACCESS_TYPE R WX PROT_TYPE RpL INITIAL_VALUE 1 1 1 1 1 1 1 1 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_...

Page 1265: ...RpL INITIAL_VALUE 1 1 1 1 1 1 1 1 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME vram_sberraddr_s2 23 16 ACCESS_TYPE R WX PROT_TYPE RpL INITIAL_VALUE 1 1 1 1 1 1 1 1 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_...

Page 1266: ...0 Interfaces with equal priorities will be round robin arbitrated BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 2...

Page 1267: ...actions All memory read transactions that are issued to the VRAM block by the 2D graphics core to fetch the display data are categorized s1_read bit3 2 vram_priority_s0_read VRAM Priority S0 Read Fixe...

Page 1268: ...ible to all registers of this address block When privilege protection is active only privileged read and write access is possible Both protections can be active at the same time BIT_OFFSET 31 30 29 28...

Page 1269: ...Value Meaning lock_key 0x5651F763 Decrements the unlock counter When the counter value is null lock protection is active Reset counter value is 1 unlock_key 0x691DB936 Increments the unlock counter M...

Page 1270: ...rved ACCESS_TYPE R0 WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11...

Page 1271: ...nlock counter 0 bit4 hpm_PrivilegeStatus High Performance Bus Matrix registers Privilege Status Current status of privilege protection Bit Description 0 inactive 1 active bit0 hpm_LockStatus High Perf...

Page 1272: ...25 24 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0...

Page 1273: ...ccess is possible Both protections can be active at the same time BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME ilaxibridge_LockUnlock ACCESS_TYPE RX W PROT_TYPE WpL INITIAL_VALUE X X X X X X X X BIT_OF...

Page 1274: ...l lock protection is active Reset counter value is 1 0x691DB936 unlock_key Increments the unlock counter Max allowed value is 15 0xAEE95CDC privilege_key Enables privilege protection Disabled after re...

Page 1275: ...OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE RX WX PROT_TYPE WpL INITIAL_VALUE X X X X X X X X BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ilaxibridge_ Freeze Status ACCESS_TYPE...

Page 1276: ...0 Series Hardware Manual Document Number 002 04852 Rev G 1275 Current status of privilege protection 0 inactive 1 active bit0 ilaxibridge_LockStatus Current status of lock protection 0 inactive unlock...

Page 1277: ...r0 must either be exactly the same as a region defined by StartMaster1 or not overlap it at all BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME ilaxibridge_StartMaster0Region0 ACCESS_TYPE R W PROT_TYPE Wp...

Page 1278: ...8 27 26 25 24 BIT_NAME ilaxibridge_EndMaster0Region0 ACCESS_TYPE R W PROT_TYPE WpL INITIAL_VALUE 0 1 0 1 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME ilaxibridge_EndMaster0Region0 ACCESS_TYPE R...

Page 1279: ...AME ilaxibridge_StartMaster0Region1 ACCESS_TYPE R W PROT_TYPE WpL INITIAL_VALUE 0 1 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME ilaxibridge_StartMaster0Region1 ACCESS_TYPE R W PROT_TYPE Wp...

Page 1280: ...8 27 26 25 24 BIT_NAME ilaxibridge_EndMaster0Region1 ACCESS_TYPE R W PROT_TYPE WpL INITIAL_VALUE 0 1 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME ilaxibridge_EndMaster0Region1 ACCESS_TYPE R...

Page 1281: ...r1 must either be exactly the same as a region defined by StartMaster0 or not overlap it at all BIT_OFFSET 31 30 29 28 27 26 25 24 BIT_NAME ilaxibridge_StartMaster1Region0 ACCESS_TYPE R W PROT_TYPE Wp...

Page 1282: ...8 27 26 25 24 BIT_NAME ilaxibridge_EndMaster1Region0 ACCESS_TYPE R W PROT_TYPE WpL INITIAL_VALUE 0 1 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME ilaxibridge_EndMaster1Region0 ACCESS_TYPE R...

Page 1283: ...AME ilaxibridge_StartMaster1Region1 ACCESS_TYPE R W PROT_TYPE WpL INITIAL_VALUE 0 1 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME ilaxibridge_StartMaster1Region1 ACCESS_TYPE R W PROT_TYPE Wp...

Page 1284: ...8 27 26 25 24 BIT_NAME ilaxibridge_EndMaster1Region1 ACCESS_TYPE R W PROT_TYPE WpL INITIAL_VALUE 0 1 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME ilaxibridge_EndMaster1Region1 ACCESS_TYPE R...

Page 1285: ...TYPE WpL INITIAL_VALUE X X X X X X X X BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE RX WX PROT_TYPE WpL INITIAL_VALUE X X X X X X X X BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME Reserved ila...

Page 1286: ...size of 8 byte 1 STEPSIZE16BYTE Interleaving step size of 16 byte 2 STEPSIZE32BYTE Interleaving step size of 32 byte 3 STEPSIZE64BYTE Interleaving step size of 64 byte 4 3 Memory Protection Unit There...

Page 1287: ...IT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE RpL WpL INITIAL_VALUE 0 0 0 0 0 0 0...

Page 1288: ...Buf1 DLBuf draweng write ACCESS_TYPE R W R W R W R W R W R W R W R W PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME draweng read store4 fetch eco4 fetch decode4 fetc...

Page 1289: ...e 3D Graphics Core 1 The error monitor is disabled for the copy area operation of the 3D Graphics Core bit21 SceneBuf4 This field indicates that the 3D Graphics Core received the error response to the...

Page 1290: ...he error monitor is enabled for the access by the drawengwrite of the 2D Graphics Core 1 The error monitor is disabled for the access by the drawengwrite of the 2D Graphics Core bit15 drawengread Bit...

Page 1291: ...or the access by the fetchdecode0 of the 2D Graphics Core 1 The error monitor is disabled for the access by the fetchdecode0 of the 2D Graphics Core bit6 store9 Bit Description 0 The error monitor is...

Page 1292: ...D Graphics Core bit1 cmdseqwrite Bit Description 0 The error monitor is enabled for the access by the cmdseqwrite of the 2D Graphics Core 1 The error monitor is disabled for the access by the cmdseqwr...

Page 1293: ...TYPE R0 WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ACCESS_TYPE R0 WX PROT_TYPE INITIAL_VALUE 0 0 0 0 0 0 0 0 BIT_OFFSET 7 6 5 4 3 2 1 0 BIT_NAME Rese...

Page 1294: ...24 BIT_NAME Reserved ACCESS_TYPE RX WX PROT_TYPE INITIAL_VALUE BIT_OFFSET 23 22 21 20 19 18 17 16 BIT_NAME Reserved ACCESS_TYPE RX WX PROT_TYPE INITIAL_VALUE BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME...

Page 1295: ...BIT_NAME ErrorSubID ACCESS_TYPE R WX PROT_TYPE INITIAL_VALUE 1 1 1 1 1 1 1 1 BIT_OFFSET 15 14 13 12 11 10 9 8 BIT_NAME Reserved ErrorID ACCESS_TYPE R0 WX R WX PROT_TYPE INITIAL_VALUE 0 0 1 1 1 1 1 1...

Page 1296: ...he 2D Graphics Core 12 FETCHDECODE4 fetchdecode4 of the 2D Graphics Core 13 FETCHECO4 fetcheco4 of the 2D Graphics Core 14 STORE4 store4 of the 2D Graphics Core 15 DRAWENGREAD drawengread of the 2D Gr...

Page 1297: ...al Document Number 002 04852 Rev G 5 References 1 2D GRAPHICS CORE PROGRAMMERS REFERENCE MANUAL 2 CHAPTER OF DDR HIGH SPEED SPI CONTROLLER 3 CHAPTER OF MEMORY PROTECTION UNIT FOR AXI 4 CHAPTER OF HYPE...

Page 1298: ...Rev G 1297 CHAPTER 34 Sound System Configuration This chapter explains the definition of sound system and configuration 1 Overview 2 Configuration and Block Diagram 3 Operation 4 Configuration and li...

Page 1299: ...naural source The other is a sound source that is in internal or external storage DMAC or CPU can transfer sound source in the embedded Flash memory or data RAM or comes from external memory via commu...

Page 1300: ...ev G 1299 2 Configuration and Block Diagram Figure 2 1 Sound waveform generator Audio DAC SWFG DMA AHB Sound mixer AHB PCM PWM FLASH RAM Internal memory I2S HSSPI I2S External memory Transfer Inputmod...

Page 1301: ...uration of Input Modules SWFG Configuration Start sound source generations configuring SWFG The generations will practically begin by means of each transfer request from the sound mixer DMAC Configura...

Page 1302: ...igure anoutput module END Notes CPU can transfer sound sources to the input channel PMIS0 to 4 of SMIX with data transfer requests of SMIX Note some sound source which is transferred from SWFG is dele...

Page 1303: ...onfiguring channels of SWFG The generations will practically begin by means of each transfer request from SMIX DMA Configuration Start additional sound source transmissions configuring a channel of DM...

Page 1304: ...cycles If this sequence is not followed PCM data requested before disabling the output module may be transferred to the output module after enabling the output module This may cause the DMA block err...

Page 1305: ...ration but only needs an operation of an output module In the case the sound source should be transferred to SMIX as same as the case of a mixing of multi sound sources The sound system cannot directl...

Page 1306: ...O of MXOCTRL register The actual setting value is the following MACRO of MXOCTRL register 0x1 Number of transfers to output destination of SMIX DATATN of MXOCTRL register must be same as FIFO empty th...

Page 1307: ...d by a data request from DMA interface of I2S I2S supports three type data transfers These are DMA Interrupt and Poling I2S must be set to DMA because the sound source is transferred from SMIX to I2S...

Page 1308: ...t be changed during the sound source translation Even if SWFG is disabled by WGCHEN register the data transfer from SWFG to SMIX is not stopped immediately Therefore the following register must not be...

Page 1309: ...IX Data transfer request interrupt of SMIX can be used as trigger for the data transfer No special configuration or limitation to be considered 5 Note Every output module doesn t support any transfer...

Page 1310: ...al Document Number 002 04852 Rev G 1309 CHAPTER 35 Base Timer Port Definition This chapter explains Base Timer Port Definition 1 Overview 2 Definition 3 Supplementation 4 Operation and Registers CODE...

Page 1311: ...MER in TraveoTM platform manual This series particularly has package external port names and function port names of base timer function input or output instead of the function port names which are def...

Page 1312: ...l Series Particular Port Name Remark TIOBn PPGu_TIN3 See RIC table TIOAn PPGu_TOUT2 See port description or POF table TIOBm PPGu_TIN1 See RIC table TIOAm PPGu_TOUT0 See port description or POF table I...

Page 1313: ...Bm Not used TIOAm PPGu_TOUT0 See port description or POF table I O mode 6 Timer start stop and simultaneous soft start mode Function Port Name in TraveoTM Platform Manual Series Particular Port Name R...

Page 1314: ...d PPGu_TIN3 are selected as input port of base timer by configuring RIC register See the chapter of PORT CONFIGURATION 3 2 Output Port Configuration PPGu_TOUT0 and PPGu_TOUT2 are selected as output po...

Page 1315: ...1314 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G CHAPTER 36 Appendix 1 Pin Status in Each CPU State 2 DMA destination list 3 Master Access Table CODE APPENDIX S6J3200 E1...

Page 1316: ...shutdown retained no influence Last state retained Last state retained Hiz Input turned off Last state retained Hiz Input turned off Last state retained Hiz Input turned off Last state retained Hiz I...

Page 1317: ...y before the shutdown retained no influence Last state retained Last state retained Hiz Input turned off Last state retained Hiz Input turned off Last state retained Hiz Input turned off Last state re...

Page 1318: ...N Outside of DMA access area Core Slave TCRAM Memory Y Y Y TCFLASH_TCM Memory Y N N TCFlash area needs write command sequence TCFLASH_AXI Memory Y N N TCFlash area needs write command sequence System...

Page 1319: ...Capture Controller Y N N Write access needs lock disabling MPU_AXI Blit Engine Y N N Write access needs lock disabling MPU_AXI Drawing Engine Y N N Write access needs lock disabling AXI Interconnect...

Page 1320: ...U Y Y Y CR calibration Y Y Y MCG_IRS Y Y Y Reload Timer Y Y Y CAN Prescaler Y Y Y M F Serial Y Y Y CAN FD Y Y Y SYSC1 SYSC1 N N N Outside of DMA access area SW WDG N N N Outside of DMA access area Mem...

Page 1321: ...Y Y FPD_LINK_CONV Y N N Write access needs lock disabling SG Y Y Y Common Peri Group 1 Reload Timer Y Y Y Base Timer Y Y Y FRT Y Y Y ICU Y Y Y OCU Y Y Y QPRC Y Y Y M F Serial Y Y Y ReloadTimer SSSR Y...

Page 1322: ...M M M Core Internal TCRAM Mem Y N TCFLASH_TCM Mem Y N TCFLASH_AXI Mem Y N Core Slave TCRAM Mem Y TCFLASH_TCM Mem Y TCFLASH_AXI Mem Y Scratch Pad RAM Memory Y Register p Y N EAM EAM Y AppS 3 APPLGRP_M...

Page 1323: ...re Displ ay CmdSeq Y N MPU_AXI Capture Controller Y N MPU_AXI Blit Engine Y N MPU_AXI Drawing Engine Y N DDRHSSPI configuration Y N AXI Interconnect Error Monitor Y N MPU_AXI 3D_Graphics_Core_Write Po...

Page 1324: ...T p N Y N MODEC p N Y N HW WDG p N Y N RTC p Y N Ext INT p Y N PD1 App Extend p Y N Backup RAM Memory Y N Backup RAM IO p Y N EICU p Y N CR calibration p Y N ALL IRQ READ p Y N RLT p Y N CAN Prescaler...

Page 1325: ...LT p Y N BT p Y N FRT p Y N ICU p Y N OCU p Y N QPRC p Y N MFS p Y N Misc Registers p Y N FPDLINK_CONV p Y N SG p Y N Common Peri Group 1 RLT p Y N BT p Y N FRT p Y N ICU p Y N OCU p Y N QPRC p Y N MF...

Page 1326: ...AC Complex Additional RLT DMAAi_ASRn p N Y N Note Y Able to access N Unable to access p Protected by PPU Accessible or not depends on PPU setting M Available MPU can be protected all of the address ar...

Page 1327: ...itial release Revision 2 0 See 1 Supplementary Information as described in CHAPTER 1 Overview 2 Document Definition Revision 3 0 See 1 Supplementary Information as described in CHAPTER 1 Overview 2 Do...

Page 1328: ...usly 210 Display output 27 Notes 32 Notes Display Output ch 0 is used for RSDS and FPD LINK LVDS as well as DRGB Digital RGB The ch 0 of the product which doesn t support FPD LINK is used for RSDS and...

Page 1329: ...0100010 33 Revision B Chip ID Revision C and D Chip ID 0x10100100 278 TEQFP256 support 30 Notes 35 TEQFP256 Notes TEQFP 256 is a package option under planning 273 CR oscillation stabilization time 33...

Page 1330: ...d Software watchdog See the platform manual in detail The product series doesn t support Watchdog Counter Monitor Output port Related register and internal circuit is implemented 225 MPU lock and unlo...

Page 1331: ...DRHSSPIn_PCC0 3 SS2CD 1 0 00 cannot be used Configure delay as 01 10 or 11 147 PD5 register configuration 40 48 SYSC0_RUNPDCFGR PD5_xEN SYSC0_PLLPDCFGR PD5_xEN SYSC0_APPPDCFGR PD5_xEN SYSC0_STSPDCFGR...

Page 1332: ...PLL SSCG maximum frequency 47 56 Note The frequency of PLLout output of PLL SSCG PLL multiplier circuit should be 800MHz or less 165 Source clock list 47 56 Source Clock Local Clock List is added 312...

Page 1333: ...Work FLASH Single Bit Error 20 Work FLASH Write Completion 78 8 TCFLASH RDY Hang up Single Bit Error 10 Work FLASH Hang up 20 Work FLASH RDY Write Enable Release Single Bit Error 308 IRQ map 66 77 17...

Page 1334: ...verterTxDOUT2 LVDS data output pin Described as TXOUT2P in FPD Link ConverterTxDOUT3 LVDS data output pin Described as TXOUT3M in FPD Link ConverterTxDOUT3 LVDS data output pin Described as TXOUT3P in...

Page 1335: ...unction configuration POF is a function to select a function to output to a port 204 The port output function configuration POF is a function to select a function to output to a port A resource which...

Page 1336: ...ODR 0 The drive capacity will be 4mA 2 1 When the PPC_PCFGR POF 2 0 value setting is 4 SDA or SCL function setting regardless of the value of the PPC_PCGR ODR 1 0 the drive capacity will be I2C Then...

Page 1337: ...PECFGR PSSPADCTRL 0 Port status hold during PSS modeAll of the GPIO except ports in VCC3 area can be kept the port status during PSS mode by System Special Setting Register SYSC0_SPECFGR The bit31 to...

Page 1338: ...ration 232 Bit6 LVDH2S Extended external low voltage detection voltage operation selection bit 254 Bit6 LVDH2S Extended external low voltage detection voltage operation selection bit Note LVDH2S shoul...

Page 1339: ...fore a serial programming operation 153 Add the section 3 Operation and 4 Registers 556 581 3 Operation of the Ethernet MAC 4 Registers 342 PCMPWM DOUBLE bit 730 bit13 DOUBLE Double Mode Enable This b...

Page 1340: ...0 W0 3 Res erved R0 W0 2 Reserved R0 W0 1 Reser ved R0 W0 0 Reserved R0 W0 bit31 28 Reserved Always write 0 to this bit The read value is 0 bit27 24 Reserved Always write 0 to this bit The read value...

Page 1341: ...ear 88 88 90 The row of Remark is added 407 DMA channel activation factors 88 89 N Base Timer ch m 1 N 1 Base Timer ch m 1 0 88 89 N Base Timer ch m 1 0 N 1 Base Timer ch m 1 371 Link information for...

Page 1342: ...mit_exceeded_or_late_collision Retry limit exceeded 419 TYPO in bit name of ETHERNET register 792 bit28 dstc_match_enable DS TC match enable bit27 12 udp_port_match_enable UDP port match enable bit11...

Page 1343: ...ith the revision digit A has 0 as the initial value After revision digit B C D E and F it has 1 as the initial value 447 PD for 3 3V I O in Block Diagram 50 50 Changed PD1 to PD2 for Power domain of 3...

Page 1344: ...e up from PSS shutdown mode I O multiplexed functions of port in VCC3 area belong to PD2 The power doesn t supply to the I O multiplexed functions during PSS shutdown mode then internal signals of the...

Page 1345: ...n Serial Ch 8 Group1 P3_04 SCK8 P3_03 SOT8 P3_05 SIN8 P3_12 MFS8_CS0 P3_16 MFS8_CS1 P3_17 MFS_CS2 P3_15 MFS_CS3 Group2 P5_03 SCK8 P5_02 SOT8 P5_04 SIN8 P5_10 MFS8_CS0 P5_15 MFS8_CS1 P5_16 MFS8_CS2 P5_...

Page 1346: ...Sound Mixer 525 526 528 537 542 549 560 507 509 511 520 530 538 546 Added the description for reserved bits 513 Correct typo of MXAHBERR register about AHB error response 564 Writing to this bit gener...

Page 1347: ...upt bit27 enable_rx_lpi_indication_interrupt 421 Ethernet Description 645 bit27 enable_receive_lpi_indication_status_bit_ change Enable Receive LPI Indication Status Bit change Always read 0 Writing 1...

Page 1348: ...tion change with SEGER 463 the bit in LCDC chapter 1026 When the bit is set to 1 a selection waveform is output from the segment output pin When the bit is set to 0 a non selection waveform is output...

Page 1349: ...ation for additional revision for revision B for after revision B CHAPTER 3 Product Description 2 Product Description Improve For convenience to understand power domain definition CHAPTER 3 Product De...

Page 1350: ...n of clearing the interrupt flag in Note CHAPTER 9 DMA Channel Activation Factors 2 Note Improved Added the note for accessing reserved area of DMAi_CMICICm CHAPTER 9 DMA Channel Activation Factors 1...

Page 1351: ...Analog to Digital Converter 5 4 Pulse Counter Control Registers ADC12Bn_PCCTRL0 to 63 Improve Corrected bit explanation of PCTNRL 4 0 ADC12Bn_PCIRQC0 PCIRQC0 bit ADC12Bn_PCIRQC0 to 1 PCIRQC bit Impro...

Page 1352: ...Improve Added the note for description of FEST 4 0 bits CHAPTER 28 LCD Controller 6 3 LCDC Control Register 1 LCR1 Improve Added the description of LCR1 configuration for not using LCDC CHAPTER 28 LC...

Page 1353: ...w 2 Document Definition Table 1 1 Improve Added the Document Code information for Application note CHAPTER 2 Function List 1 Function List Enhance Updated Description and Remark for System RAM size en...

Page 1354: ...alue Improve Added the initial value and access type information for PLL and LVD register CHAPTER 21 Ethernet MAC 3 1 8 Priority Queuing in the Ethernet MAC DMA Improve Added explanation that lower pr...

Page 1355: ...of G_SSEL and M_SSEL port CHAPTER 12 State Transition 4 Changes to PSS and RUN Figure 4 1 Enhance Added revision version P to the note of Figure 4 1 G CHAPTER 3 Product Description 3 3 Register Initi...

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