Cypress S6J3200 Series, Manual

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CHAPTER 30:FPD-Link Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1133
4.6.
GDC Control Register (GDCCR)
Controls GDC SUBSYSTEM reset.
Depending on the GDC SUBSYSTEM status when the reset is executed, a system backup may be
performed. Control reset based on GDC SUBSYSTEM specifications.
REGISTER_NAME GDCCR
OFFSET 0x40
ACCESS_SIZE B H W
MULTIPLE 0:31
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
ACCESS_TYPE R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0
PROT_TYPE Wp
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
ACCESS_TYPE R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0
PROT_TYPE Wp
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
ACCESS_TYPE R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0
PROT_TYPE Wp
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME Reserved Reserved Reserved Reserved Reserved Reserved Reserved GRST
ACCESS_TYPE R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R0,W0 R/W
PROT_TYPE Wp
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:1] Reserved
Always write "0" to this bit. The read value is "0".
[bit0] GRST :GDC Reset
This bit controls reset signal of GDC.
Use software control to cancel a reset following the reset setting. The reset time should be in
accordance with the requirements of GDC.