CHAPTER 21:Ethernet MAC
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
593
particular queue to route it to. The interface to the screeners is via two banks of programmable registers,
Screening Type 1 registers and Screening Type 2 registers.
Screening Type 1 registers allow routing received frames based on particular IP and UDP fields extracted
from the received frames. Specifically these fields are DS (Differentiated Services field of IPv4 frames),
TC (Traffic Class field of IPv6 frames) and/or the UDP destination port. These fields are compared
against the values stored in each of the Screening Type 1 registers. If the result of this comparison is
positive, then the received frame is routed to the priority queue specified in that Screening Type 1 register.
Refer to Screening Type 1 register description for further programming details.
Screening Type 2 registers operate independently of Screening Type 1 registers and offer additional
match capabilities, extending the capabilities into vendor specific protocols. The Type 2 screening allows
a screen to be configured that is the combination of all or any of the following comparisons.
1.
An enabled field VLAN Priority. A VLAN Priority match will be performed if the VLAN priority
enable is set. The extracted priority field in the VLAN header is compared against 3 bits within the
Screening Type 2 register itself.
2.
An enabled field EtherType. The EtherType field inside the Screening Type 2 register maps to 1 of
8 EtherType Match registers. The extracted EtherType is compared against the EtherType 2
register designated by this EtherType field.
3.
An enabled field Compare A.
4.
An enabled field Compare B.
5.
An enabled field Compare C.
Compare A, Compare B, and Compare C each have an Enable bit and Compare Register field. The
Compare Register field is a pointer to a configured OFFSET, VALUE, and MASK. If enabled the compare
is true if the data at the OFFSET into the frame, ANDed with the MASK value is equal to the COMPARE
value. A 16-bit word comparison is done. The byte at the OFFSET number of bytes from the index start is
compared through bits [15:8] of the configured VALUE and MASK. The OFFSET can be configured to be
from 0 to 127 bytes from either the start of the frame, the byte following the EtherType field, the byte
following the end of the IP header (IPv4 or IPv6) or the byte following the end of the TCP/UDP header.
Note the logic to decode the IP header or the TCP/UDP header is reused from the TCP/UDP/IP
checksum offload logic and therefore has the same restrictions on use (the main limitation is that IP
fragmentation is not supported). Refer to Checksum Offload for IP, TCP, and UDP section for further
details. The Compare Register field points to a single pool of 32 compare registers. Compare A, Compare
B, and Compare C use a common set of compare registers.
Note Compare A, Compare B, and Compare C together allow matching against an arbitrary 48-bits of
data and so can be used to match against a MAC address.
All enabled comparisons are ANDed together to form the overall Type 2 screener match. Refer to
Screening Type 2 register descriptions for further programming details.
Each screener register is programmable vie the AHB Slave Interface. Although this is not recommended,
it is possible that more than one screener register will be programmed to match against a single frame. If
this happens there are 2 cases to consider.
1.
If a received frame matches against multiple screeners of the same type, then the frame will route
to the queue mapped by the screener located at the lowest numeric offset address. E.g. if
Screening Type 2 Register 0 and Screening Type 2 Register 1 both match, then the frame will be
routed to the queue identified in queue_number[3:0] of Screening Type 2 Register 0.
2.
If a received frame matches against a Screening Type 2 and a Screening Type 1, then the
Screening Type 1 will take precedence.
When a screener is matched, the received frame will be routed to a queue defined inside bits [3:0] of the
screener register (ETHERNETn_screening_type_1_register_i or
ETHERNETn_screening_type_2_register_i). Unmatched frames are routed to Queue 0.
Summary of Contents for S6J3200 Series
Page 1041: ...CHAPTER 28 LCD Controller 1040 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G...
Page 1044: ...CHAPTER 28 LCD Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1043...
Page 1047: ...CHAPTER 28 LCD Controller 1046 S6J3200 Series Hardware Manual Document Number 002 04852 Rev G...
Page 1050: ...CHAPTER 28 LCD Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1049...
Page 1084: ...CHAPTER 28 LCD Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1083...
Page 1086: ...CHAPTER 28 LCD Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1085...
Page 1088: ...CHAPTER 28 LCD Controller S6J3200 Series Hardware Manual Document Number 002 04852 Rev G 1087...