Cypress S6J3200 Series, Manual

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CHAPTER 29:Indicator PWM
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1105
[bit7] DOP: Count status bit
Setting the STRG bit to "1" while the CTEN bit is "1" will immediately make this bit "1".
The read value for this bit is "1" while a PWM timer count is in progress.
The read value for this bit is "0" while the PWM timer is stopped.
The read value for this bit is "0" while the PWM timer count is stopped after the CTEN bit is set to "0".
Set this bit to "0" before selecting a timer clock (ITMCR:CKS2-0), or configuring PWM cycle (IPCSR) or
PWM duty (IPDUT) settings. These settings are ignored if they are configured while this bit is "1".
Bit Description
0 Timer count stopped
1 Timer count operation in progress
[bit6:2] Reserved
These are reserved bits. Writing data to these bits has no effect on operation.
[bit1] CTEN: Count operation enable bit
This bit enables operation of the down counter.
If "0" is written to this bit while a counter operation is in progress (DOP bit is "1"), a stop request will be
output for the counter.
Counter stop can be checked by confirming that the counter status bit (DOP bit) is "0".
After CTEN bit is set to 0, if you re-set CTEN bit to "1", you must check DOP bit is "0".
Bit Description
0 Request stop
1 Enable operation.
[bit0] STRG: Software trigger bit
If "1" is written to the STRG bit when the CTEN bit is "1", a software trigger is applied.
The read value of the STRG bit is always "0".
Notes:
−
Even if "1" is written to the CTEN and STRG bits at the same time, a software trigger is applied.
−
When consecutively setting STRG bits, allow a time of at least 8T (T: main oscillator clock cycle)
between settings. Failure to do so may result in a setting not being reflected.
Bit Description
0 Disabled
1 Startup by software