Cypress S6J3200 Series, Manual

Page: 332 / 1355

CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 331
5.15.2.
Pulse Counter Interrupt Enable Register (ADC12Bn_PCIRQE1)
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME PCIRQE63 PCIRQE62 PCIRQE61 PCIRQE60 PCIRQE59 PCIRQE58 PCIRQE57 PCIRQE56
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME PCIRQE55 PCIRQE54 PCIRQE53 PCIRQE52 PCIRQE51 PCIRQE50 PCIRQE49 PCIRQE48
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME PCIRQE47 PCIRQE46 PCIRQE45 PCIRQE44 PCIRQE43 PCIRQE42 PCIRQE41 PCIRQE40
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME PCIRQE39 PCIRQE38 PCIRQE37 PCIRQE36 PCIRQE35 PCIRQE34 PCIRQE33 PCIRQE32
ACCESS_TYPE R/W R/W R/W R/W R/W R/W R/W R/W
PROT_TYPE
INITIAL_VALUE 0 0 0 0 0 0 0 0
[bit31:0] PCIRQE63 to 32 : Pulse Counter Interrupt Enable bits
Bit Description
0 Pulse counter interrupt is disabled.
1 Pulse counter interrupt is enabled.
Pulse counter interrupt is issued when this bit is "1" and the corresponding interrupt flags
ADC12Bn_PCIRQ1.PCIRQ63 to 32 and ADC12Bn_CHSTAT32 to 63.PCIRQ are set to "1".