Cypress S6J3200 Series, Manual

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CHAPTER 29:Indicator PWM
1102 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
[bit14:12] CKS2 to CKS0: Count clock selection bits
These bits select a count clock for the 16-bit down counter.
Stop the timer (ICNTCR:DOP[bit]=0) before changing the count clock.
CKS2 CKS1 CKS0 Description
0 0 0 Main oscillator clock
0 0 1 Main oscillator clock divided by 16
0 1 0 Main oscillator clock divided by 64
0 1 1 Main oscillator clock divided by 256
1 0 0 Main oscillator clock divided by 1024
1 0 1 Main oscillator clock divided by 2048
1 1 0 Main oscillator clock
1 1 1 Main oscillator clock
[bit11] Reserved
This is a reserved bit.
Writing data to these bits has no effect on operation.
[bit10] PMSK: Pulse output mask bit
This bit controls the output waveform level of the PWM output waveform.
When the bit is "0", the PWM waveform is output as is.
When the bit is "1", PWM output is masked to L output regardless of the cycle or duty setting value.
Note:
−
If the output polarity specification bit (OSEL) in the timer control register (lower byte of ITMCR) is
set for inverted output, setting the PMSK bit to "1" results in masking to H output.
Bit Description
0 Normal output
1 Fixed at L output
[bit9:4] Reserved
These are reserved bits. Writing data to these bits has no effect on operation.
[bit3] OSEL: Output polarity specification bit
This bit sets the PWM output polarity.
Polarity After Reset Duty Match Underflow
Normal "L" output
Inverse "H" output