Cypress S6J3200 Series, Manual

Page: 235 / 1355

CHAPTER 12:State Transition
234 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Figure3-3 Operation Mode Fetch Timing Chart
Hard Reset (other Reset Factor)
Reset Factor
RESET
Internal Reset
VCC12 H
PSC1 H
Internal Clock
Internal Clock output enable
Internal Clock STOP request
Internal Clock STOP response
Regulator of flash memory Reset H
SYSC(SYStem Controller0) Reset RESET
SYSC(SYStem Controller0) Clock
CPU operating
Internal Power Domain state ON
Internal Power Domain Reset H
processing description
User
program operating
clock stop wait
(Fast-CR*
Source
Clock*3cycle)
Reset
and
Reset Factor release wait
Regulator of flash
stabilization wait(skip)
Mode evaluation
and
Security
evaluation
and
Internal reset
release
BootROM
program operating
User
program operating
Soft Reset
Reset Factor
Internal Reset RESET
Internal Clock
Internal Clock output enable H
VCC12 H
PSC1 H
Internal Clock STOP request
Internal Clock STOP response
Regulator of flash memory Reset H
SYSC(SYStem Controller0) Reset H
SYSC(SYStem Controller0) Clock
CPU operating
Internal Power Domain state ON
Internal Power Domain Reset H
processing description
User
program operating
clock stop wait
(Fast-CR*
Source
Clock*3cycle)
Reset
and
Reset Factor
release wait
Regulator of flash
stabilization
wait(skip)
User
program operating
BootROM
program operating
Mode evaluation
and
Security evaluation
and
Internal reset
release