Cypress S6J3200 Series, Manual

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CHAPTER 21:Ethernet MAC
732 S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
4.77.
Frame Check Sequence Errors Register (ETHERNETn_fcs_errors)
Description of Frame Check Sequence Errors register is shown.
REGISTER_NAME ETHERNETn_fcs_errors
OFFSET 0x190
ACCESS_SIZE W
MULTIPLE
NUMERIC_TYPE
OTHER
BIT_OFFSET 31 30 29 28 27 26 25 24
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 23 22 21 20 19 18 17 16
BIT_NAME Reserved
ACCESS_TYPE R0,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
BIT_OFFSET 15 14 13 12 11 10 9 8
BIT_NAME Reserved count[9:8]
ACCESS_TYPE R0,WX R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00 0x0
BIT_OFFSET 7 6 5 4 3 2 1 0
BIT_NAME count[7:0]
ACCESS_TYPE R,WX
PROT_TYPE Wp
INITIAL_VALUE 0x00
[bit31:10] Reserved
Always read "0". Writing has no effect.
[bit9:0] count: Frame check sequence errors
A 10-bit register counting frames that are an integral number of bytes, have bad CRC and are between
64 and 1518 bytes in length (1536 if bit 8 set in Network Configuration register, 10240 bytes if bit 3 is
set in the Network Configuration register). This register is also incremented if a symbol error is detected
and the frame is of valid length and has an integral number of bytes. This register is incremented for a
frame with bad FCS, regardless of whether it is copied to memory due to ignore FCS mode being
enabled in bit 26 of the Network Configuration register.