CHAPTER 33:Graphics Subsystem
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
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The field dsp0/1_ClockDivider can be updated at any point in time (e.g. also when dsp0/1_ClockEnable
is set to 1 and display clock is output). The display clock generation will then update the generated clocks
frequency in such a manner that continuity of the generated display clock is guaranteed (e.g. no glitches
are produced).
In addition to enabling the dsp0/1_ClockEnable setting the dsp0/1_SoftwareReset should be set to 0 to
release
the reset of the display logic and make it functional. Write dsp0/1_SoftwareReset to 1 only when the
display engine has been completely shut down. Other use of the dsp0/1_SoftwareReset is applicable to
debug purposes only.
Note that use of the generated display clock for display clock output is only allowed if the 2D Graphics
Core DisEngCfg
ClockCtrl setting is set to DIV2.
Display Clock Shift
To allow to create sufficient margin for setup and hold times at the external device the output display clock
can be shifted. The dsp0/1_ClockOffset setting can shift the display clock up to (not including) 180
degrees in reference clock period steps. To achieve shifts larger or equal to 180 degrees the
dsp0/1_ClockInvert setting can be used in addition to add 180 degrees to the shift achieved with
dsp0/1_ClockOffset.
It is recommended to verify the achieved margins in setup and hold times by using e.g. an oscilloscope.
Note that the generated display clock periods can jitter from cycle to cycle by the reference clock period
due to the way the fixed point clock division works.
The dsp0/1_ClockOffset and dsp0/1_ClockInvert settings must not be changed when
dsp0/1_ClockEnable is set to 1, otherwise corruption of displayed content is possible.
Summary of Contents for S6J3200 Series
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