Cypress S6J3200 Series, Manual

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CHAPTER 33:Graphics Subsystem
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 1187
2.2.
The 3D Graphics Core
For the detailed information of the 3D Graphics Core, refer to [5].
2.3.
The 2D Graphics Core
For the detailed information of the 2D Graphics Core, refer to [1].
2.4.
High Performance Bus Matrix
The modules inside the subsystem are connected each other, via local bus line. It has 64 bits data and 32
bits address width.
2.5.
Memory Protection Units ( MPU )
For safety reasons, access by write bus masters is protected by Memory Protection Units. For functional
details of the Memory Protection Unit, refer to [3].
Affected write masters are

Blit Engine

Drawing Engine

Capture Controller

3D Graphics Core ( Scene Buffer access 1 )

3D Graphics Core ( Scene Buffer access 2 )

3D Graphics Core ( Copy Area operation )
The following write masters do not have an Memory Protection Units:

Main system port;
Use the Memory Protection Unit in the main system to prevent the illegal access into the Graphics
Subsystem..

Command Sequencer –
The unit uses the port for write access to its command buffer only. The position and size of this buffer is
a static configuration and protected by a lock mechanism, so there is no need for additional protection
by a Memory Protection Unit.
2.6.
Bus Monitor
A bus monitor observes all bus transactions in order to detect error responses. It can store the ID of the
first master that received an error response and can trigger an interrupt.
This feature is particularly useful in the context of this subsystem, because the masters of the 2D
Graphics Core do not implement a bus error detection, but simply ignore them.