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CHAPTER 21:Ethernet MAC
588
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G
Bit
Function
Word 3
31:4
Unused
3:0
Timestamp seconds [5:2] (see Note1)
Note 1: The timestamp mode is controlled using the TX BD Control register
(ETHERNETn_tx_bd_control).
To transmit frames, the buffer descriptors must be initialized by writing an appropriate byte address to bits
[31:0] in the first word (Word 0) of each descriptor list entry.
The second word (Word 1) of the transmit buffer descriptor is initialized with control information that
indicates the length of the frame, whether or not the MAC is to append CRC and whether the buffer is the
last buffer in the frame.
After transmission the status bits are written back to the second word of the first buffer along with the
“Used” bit. Bit 31 is the “Used” bit which must be “0” when the control word is read if transmission is to
take place. It is written to “1” once the frame has been transmitted. Bits [29:20] indicate various transmit
error conditions. Bit 23 indicates a valid timestamp has been capture in the BD. Bit 30 is the “Wrap” bit
which can be set for any buffer within a frame. If no wrap bit is encountered the queue pointer continues
to increment.
The TX Buffer Queue Base Address register can only be updated whilst transmission is disabled or
halted; otherwise any attempted write will be ignored. When transmission is halted the transmit buffer
queue pointer will maintain its value. Therefore when transmission is restarted the next descriptor read
from the queue will be from immediately after the last successfully transmitted frame. Whilst transmit is
disabled (ETHERNETn_network_control[3] = 0), the transmit buffer queue pointer resets to point to the
address indicated by the TX Buffer Queue Base Address register. Note that disabling receive does not
have the same effect on the receive buffer queue pointer.
Once the transmit queue is initialized, transmit is activated by writing to the transmit start bit
(ETHERNETn_network_control[9]). Transmit is halted when a buffer descriptor with its “Used” bit set is
read, a transmit error occurs, or by writing to the transmit halt bit of the Network Control register
(ETHERNETn_network_control[10]). Transmission is suspended if a pause frame is received while the
pause enable bit is set in the Network Configuration register (ETHERNETn_network_configuration[13]).
Rewriting the start bit while transmission is active is allowed. This is implemented with a transmit_go
variable which is readable in the Transmit Status register at bit location 3. The transmit_go variable is
reset when:
1. Transmit is disabled
2. A buffer descriptor with its ownership bit set is read.
3. Bit 10, tx_halt_clk, of the Network Control register is written.
4. There is a transmit error such as too many retries or a transmit under run.
To set transmit_go write to bit 9, tx_start_clk, of the Network Control register. Transmit halt does not take
effect until any ongoing transmit finishes.
If the Ethernet MAC DMA is configured for packet buffer partial store and forward mode and a collision
occurs during transmission of a multi-buffer frame, transmission will automatically restart from the first
buffer of the frame. For packet buffer mode, the entire contents of the frame are read into the TX Packet
Buffer Memory, so the retry attempt will be replayed directly from the TX Packet Buffer Memory rather
than having to re-fetch through AXI Master Interface.
Summary of Contents for S6J3200 Series
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