Cypress S6J3200 Series, Manual

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CHAPTER 15:12-/10-/8-bit Analog to Digital Converter
S6J3200 Series Hardware Manual Document Number: 002-04852 Rev. *G 259
3.2.
Logical Channel Mapping to Analog Input Signals
64 logical channels are mapped to up to 64 analog input signals that need to be converted into the digital
values. The mapping is done over ADC12Bn_CHCTRL0 to 63.CHNUM configuration fields in the way
that CHNUM value controls the number of the analog input signal AN, that is propagated to the A/D
Converter input in case the logical channel is converted.
Figure 3-2 illustrates an example of possible logical channel mapping to analog inputs. Each logical
channel is mapped to exactly one analog input and it is allowed to map several logical channels to the
same analog input (logical channels 4, 5, 6 and 62 are mapped to the analog input AN8).
Figure 3-2 Example of Logical Channel Mapping to Analog Inputs
The described way of logical channel organization provides following benefits:
−
Configurable grouping and consecutive conversion of channels independent on physical pin order.
−
Mapping of several logical channels to the same analog input allows repetitive conversion of the
same analog input with only one interrupt at the end.
3.3.
Logical Channel Data Protection Function
Every logical channel has its own conversion data register ADC12Bn_CD. They are written by hardware
at the end of conversion of the dedicated channel. The CPU can read the data registers any time. If a
conversion is finished and the data of the previous conversion of the same channel has not been read out,
previous data could be overwritten and previous conversion result lost. To avoid this, the data protection
function can be enabled so that the next conversion of this logical channel is not started until the previous
data has been read out. The data protection function is controlled by the corresponding
ADC12Bn_CHCTRL0 to 63.DP bits:
−
If for some logical channel the dedicated ADC12Bn_CHCTRLi.DP bit is equal to "0", then
conversion is continued and former conversion data are overwritten.
−
In case of a regular logical channel, if the dedicated ADC12Bn_CHCTRLi.DP bit is equal to "1" and
conversion done interrupt flag is set to "1", this logical channel cannot be selected for the
conversion even though its trigger status may be set. The channel can be selected for conversion
again after its conversion done interrupt flag has been cleared, e.g. by reading the conversion data
register.
−
In case of a multiple conversion logical channel
−
if the dedicated DP bit is equal to "1" and conversion done interrupt flag is set to "1" or
−
if the dedicated DP bit is equal to "1", group interrupted interrupt flag is set to "1", group
interrupted interrupt is enabled and multiple conversions are already started, then the
channel cannot be selected for conversion until its conversion done interrupt flag or group
interrupted interrupt flag have been cleared.
Logical channel number
CHNUM bit field setting
Analog input signal AN52 AN14 AN63 AN0 AN8 AN8 AN32
...
AN1 AN2 AN3 AN28 AN8 AN4 AN8
0 1 2 3 4 5 6 7
...
58 59 60 61 62 63
52 14 63 0 8 8 8 32
...
1 2 3 28 8 4